# US 2019/0318774 A1 · Memory device with strong polarization coupling

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- Number: US 2019/0318774 A1
- Document ID: US20190318774A1
- Status: Published application
- Kind: A1
- Application number: 16/142,944
- Filed: 2018-09-26
- Published: 2019-10-17
- Earliest claimed: 2018-04-16
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., LTD.
- Inventors: Jorge A. Kittl; Borna J. Obradovic; Ryan M. Hatcher; Titash Rakshit
- Web page: https://patentgrep.com/patent/US20190318774A1

## CPC

- G11C 11/221: {using ferroelectric capacitors}
- H10D 1/684: {the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers}
- G11C 11/2259: {Cell access}
- H10B 53/30: characterised by the memory core region
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device and method for providing the semiconductor memory device are described. The semiconductor memory device includes a ferroelectric capacitor. The ferroelectric capacitor includes a first electrode, a second electrode and a multilayer insulator structure between the first and second electrodes. The multilayer insulator structure includes at least one ferroelectric layer and at least one dielectric layer. The at least one ferroelectric layer and the at least one dielectric layer share at least one interface and have a strong polarization coupling.

## Claims

### Claim 1

A semiconductor memory device comprising:
a ferroelectric capacitor including a first electrode, a second electrode and a multilayer insulator structure between the first electrode and the second electrode, the multilayer insulator structure including at least one ferroelectric layer and at least one dielectric layer, the at least one ferroelectric layer and the at least one dielectric layer sharing at least one interface and having a strong polarization coupling.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1 wherein the at least one ferroelectric layer has a first polarization, the at least one dielectric layer has a second polarization, the strong polarization coupling being such that the first polarization and the second polarization are within twenty percent of each other.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2 wherein the first polarization and the second polarization are within ten percent of each other.

### Claim 4 (depends on 2)

The semiconductor memory device of claim 2 wherein the first polarization and the second polarization are within two percent of each other.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1 wherein the at least one ferroelectric layer includes a first ferroelectric layer, the at least one dielectric layer includes a first dielectric layer, the first ferroelectric layer sharing a first interface of the at least one interface with the first dielectric layer, the multilayer gate insulator structure having an interface polarization coupling constant (λ) that is at least one of greater than the negative one multiplied by αFE multiplied by tFE (λ>−αFE*tFE) and greater than the absolute value of αFE multiplied by tFE (λ>|αFE|*tFE) where αFE is a material parameter of the ferroelectric layer and tFE is a thickness of the ferroelectric layer.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1 wherein the at least one ferroelectric layer includes a first ferroelectric layer, the at least one dielectric layer includes a first dielectric layer and a second dielectric layer, the first ferroelectric layer sharing a first interface of the at least one interface with the first dielectric layer, the first ferroelectric layer sharing a second interface of the at least one interface with the second dielectric layer, the multilayer gate insulator structure having a first interface polarization coupling constant (λ1) for the first interface and a second interface polarization coupling constant (λ2) for the second interface such that a sum of the first and second interface polarization constants is at least one of greater than the negative one multiplied by αFE multiplied by tFE (λ1+λ2>−αFE*tFE) and greater than the absolute value of αFE multiplied by tFE (λ1+λ2>|αFE|*tFE) where αFE is a material parameter of the ferroelectric layer and tFE is a thickness of the ferroelectric layer.

### Claim 7 (depends on 1)

The semiconductor memory device of claim 1 wherein the multilayer insulator structure has a total thickness of the at least one ferroelectric layer (dFE), a total thickness of the at least one dielectric layer (dDE), an interface polarization coupling constant (λ), αFE is a material parameter of the at least one ferroelectric layer and a ferroelectric permeability (χ) such that:
αDEdDE>|αFE|dFEλ/(λ−|αFE|dFE)
where the total thickness of the at least one ferroelectric layer is a first sum of at least one thickness for each of the at least one ferroelectric layer, the total thickness of the at least one dielectric layer is a second sum of at least one thickness for each of the at least one dielectric layer.

### Claim 8 (depends on 1)

The semiconductor memory device of claim 1 wherein the at least one dielectric layer includes at least one of a perovskite oxide, SrTiO3, Al2O3, SiO2 and SiON and wherein the at least one ferroelectric layer includes at least one of a ferroelectric perovskite, (Pb(Zr—Ti)O3), BaTiO3, at least one HfO2-based ferroelectric material, Si-doped HfO2 and ferroelectric (Hf—Zr)O2.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1 wherein the at least one ferroelectric layer is epitaxial to the at least one dielectric layer.

### Claim 10 (depends on 1)

The semiconductor memory device of claim 1 wherein the semiconductor memory device is a dynamic random-access memory cell.

### Claim 11 (depends on 10)

The semiconductor memory device of claim 10 further comprising:
a selection transistor coupled with the ferroelectric capacitor.

### Claim 12 (depends on 1)

The semiconductor memory device of claim 1 wherein at least one of the at least one ferroelectric layer has at least one electrical polarization that is free from hysteresis.

### Claim 13

A semiconductor memory device comprising:
a plurality of memory cells, each of the plurality of memory cells including a ferroelectric capacitor, the ferroelectric capacitor having a first electrode, a second electrode and at least one multilayer insulator structure between the first electrode and the second electrode, the at least one multilayer insulator structure including at least one ferroelectric layer and at least one dielectric layer, the at least one ferroelectric layer and the at least one dielectric layer sharing at least one interface and having a strong polarization coupling.

### Claim 14 (depends on 13)

The semiconductor memory device of claim 13 wherein the at least one ferroelectric layer has a first polarization, the at least one dielectric layer has a second polarization, the strong polarization coupling being such that the first polarization and the second polarization being within twenty percent of each other.

### Claim 15 (depends on 13)

The semiconductor memory device of claim 13 wherein the first polarization and the second polarization are within ten percent of each other.

### Claim 16 (depends on 12)

The semiconductor memory device of claim 12 wherein the semiconductor device is a dynamic random-access memory (DRAM), the at least one dielectric layer includes at least one of a perovskite oxide, SrTiO3, Al2O3, SiO2 and SiON, and the at least one ferroelectric layer include at least one of a ferroelectric perovskite, (Pb(Zr—Ti)O3), BaTiO3, at least one HfO2-based ferroelectric material, Si-doped HfO2 and ferroelectric (Hf—Zr)O2.

### Claim 17 (depends on 1)

The semiconductor device of claim 1 wherein the at least one ferroelectric layer is epitaxial to the at least one dielectric layer and has at least one electrical polarization that is free from hysteresis.

### Claim 18

A method for providing a semiconductor device comprising:
providing a first electrode layer;
providing a multilayer insulator structure on the first electrode layer including
providing at least one ferroelectric layer; and
providing at least one dielectric layer such that the at least one ferroelectric layer and the at least one dielectric layer share at least one interface and have a strong polarization coupling;
providing a second electrode, the multilayer insulator structure residing between the second electrode and the first electrode.

### Claim 19 (depends on 18)

The method of claim 18 wherein the at least one ferroelectric layer has a first polarization, the at least one dielectric layer has a second polarization, the strong polarization coupling being such that the first polarization and the second polarization are within twenty percent of each other.

### Claim 20 (depends on 18)

The method of claim 18 wherein the multilayer gate insulator structure has a total thickness of the at least one ferroelectric layer (dFE), a total thickness of the at least one dielectric layer (dDE), an interface polarization coupling constant (λ), αFE is a material parameter of the at least one ferroelectric layer and a ferroelectric permeability (χ) such that:
αDEdDE>|αFE|dFEλ/(λ−|αFE|dFE)
where the total thickness of the at least one ferroelectric layer is a first sum of at least one thickness for each of the at least one ferroelectric layer, the total thickness of the at least one dielectric layer is a second sum of at least one thickness for each of the at least one dielectric layer.