# US 2019/0318700 A1 · Display device and method for driving the same

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- Number: US 2019/0318700 A1
- Document ID: US20190318700A1
- Status: Published application
- Kind: A1
- Application number: 16/380,629
- Filed: 2019-04-10
- Published: 2019-10-17
- Earliest claimed: 2018-04-12
- Assignees: Sharp Kabushiki Kaisha
- Applicants: Sharp Kabushiki Kaisha
- Inventors: YASUAKI IWASE; TAKUYA WATANABE; AKIRA TAGAWA; TAKATSUGU KUSUMI; YOHEI TAKEUCHI
- Web page: https://patentgrep.com/patent/US20190318700A1

## CPC

- G09G 3/3614: {Control of polarity reversal in general}
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 3/3677: {suitable for active matrices only}
- G09G 3/3688: {suitable for active matrices only}
- G09G 2310/0213: controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A precharge circuit configured to precharge source bus lines is provided in a display device employing an SSD method. In the case where an n-channel TFT is employed, the precharge circuit applies a precharge voltage to the source bus line connected to the pixel formation portions to be subjected to data writing of a positive polarity, before a video signal is applied to the source bus line. In each horizontal scanning period, an SSD circuit switches the source bus line of a connection. destination of a data output line so that the video signal is applied to the source bus line connected to the pixel formation portions to be subjected to the data writing of a negative polarity relatively prior to the source bus line connected to the pixel formation portions to be subjected to the data writing of the positive polarity.

## Claims

### Claim 1

A display device comprising a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, a plurality of pixel formation portions arranged corresponding to respective intersections between the plurality of video signal lines and the plurality of scanning signal lines, and a scanning signal line drive circuit configured to drive the plurality of scanning signal lines, the display device comprising:
a video signal line drive circuit configured to output a video signal to a data output line in a time division manner in each horizontal scanning period, the data output line corresponding to each video signal line group obtained by grouping the plurality of video signal lines with K video signal lines set as one group, where K is an integer of two or more;
a connection switching circuit including a connection control transistor configured to control an electrical connection state between each of the video signal lines and the data output line corresponding thereto, the connection switching circuit configured to switch a connection destination of the data output line corresponding to each of the video signal line groups among the K video signal lines configuring each of the video signal line groups in a time division manner in each of the horizontal scanning periods; and
a preliminary charging circuit configured to apply a preliminary charging voltage to the plurality of video signal lines,
wherein in a case where the connection control transistor is of an n-channel type,
in each of the horizontal scanning periods, the preliminary charging circuit applies the preliminary charging voltage to the video signal line connected to the pixel formation portions to be subjected to data writing of a positive polarity before the video signal outputted from the video signal line drive circuit is applied to the video signal line, and
in each of the horizontal scanning periods, the connection switching circuit switches the video signal line of the connection destination of the data output line so that the video signal outputted from the video signal line drive circuit is applied to the video signal line connected to the pixel formation portions to be subjected to the data writing of a negative polarity relatively prior to the video signal line connected to the pixel formation portions to be subjected to the data writing of the positive polarity,
in a case where the connection control transistor is of a p-channel type,
in each of the horizontal scanning periods, the preliminary charging circuit applies the preliminary charging voltage to the video signal line connected to the pixel formation portions to subjected to the data writing of the negative polarity before the video signal outputted from the video signal line drive circuit is applied to the video signal line, and
in each of the horizontal scanning period, the connection switching circuit switches the video signal line of the connection destination of the data output line so that the video signal outputted from the video signal line drive circuit is applied to the video signal line connected to the pixel formation portions to be subjected to the data writing of the positive polarity relatively prior to the video signal line connected to the pixel formation portions to be subjected to the data writing of the negative polarity.

### Claim 2 (depends on 1)

The display device according to claim 1, wherein
a polarity of the data writing in each of the pixel formation portions is switched between a positive polarity and a negative polarity every frame, and
the video signal line drive circuit differentiates output order of K pieces of data between in an odd-numbered frame and in an even-numbered frame, the K pieces of data being outputted as the video signal to the data output line in each of the horizontal scanning periods.

### Claim 3

The display device according to clam 2, wherein
the K is two, and
when two video signal lines configuring each of the video signal line groups are defined as a first video signal line and a second video signal line,
in a former half of the odd-numbered frame, the video signal outputted from the video signal line drive circuit is applied to the first video signal line, and the preliminary charging voltage is applied to the second video signal line,
in a latter half of the odd-numbered frame, the video signal outputted from the video signal line drive circuit is applied to the second video signal line,
in a former half of the even-numbered frame, the video signal outputted from the video signal line drive circuit is applied to the second video signal line, and the preliminary charging voltage is applied to the first video signal line, and
in a latter half of the even-numbered. frame, the video signal outputted from the video signal line drive circuit is applied to the first video signal line.

### Claim 4 (depends on 2)

The display device according to claim 2, wherein
the K is three,
when six video signal lines are one driving unit, and
the six video signal lines configuring each of the driving units are defined as a first video signal line, a second video signal line, third video signal line, a fourth video signal line, a fifth video signal line, and a sixth video signal line, and three periods obtained by dividing each of the horizontal scanning periods into three are defined as a first period, second period, and a third period,
in the first period of the odd-numbered frame, the video signal outputted from the video signal line drive circuit is applied to the first video signal line and the third video signal line, and the preliminary charging voltage is applied to at least the second video signal line,
in the second period of the odd-numbered frame, the video signal outputted from the video signal line drive circuit is applied to the second video signal line and the fifth video signal line, and the preliminary charging voltage is applied to the fourth video signal line and the sixth video signal line,
in the third period of the odd-numbered frame, the video signal outputted from the video signal line drive circuit is applied to the fourth video signal line and the sixth video signal line,
in the first period of the even-numbered frame, the video signal outputted from the video signal line drive circuit is applied to the fourth video signal line and the sixth video signal line, and the preliminary charging voltage is applied to at least the fifth video signal line,
in the second period of the even-numbered frame, the video signal outputted from the video signal line drive circuit is applied to the second video signal line and the fifth video signal line, and the preliminary charging voltage is applied to the first video signal line and the third video signal line, and
in the third period of the even-numbered frame, the video signal outputted from the video signal line drive circuit is applied to the first video signal line and the third video signal line.

### Claim 5 (depends on 1)

The display device according to claim 1, wherein
in the case where the connection control transistor is of the n-channel type, the preliminary charging voltage is set to a maximum voltage of the video signal when the data writing of the positive polarity is performed, and
in the case where the connection control transistor is of the p-channel type, the preliminary charging voltage is set to a minimum voltage of the video signal when the data writing of the negative polarity is performed.

### Claim 6 (depends on 1)

The display device according to claim 1, wherein
the connection switching circuit is arranged in a region between the plurality of pixel formation portions and the video signal line drive circuit, and
the preliminary charging circuit is arranged on an opposite side of the connection switching circuit with respect to the plurality of pixel formation portions.

### Claim 7 (depends on 1)

The display device according to claim 1, wherein the video signal line drive circuit, the connection switching circuit, and the preliminary charging circuit are arranged on a same side with respect to the plurality of pixel formation portions.

### Claim 8

A method for driving a display device including a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, a plurality of pixel formation portions arranged corresponding to respective intersections between the plurality of video signal lines and the plurality of scanning signal lines, a scanning signal line drive circuit configured to drive the plurality of scanning signal lines, a video signal line drive circuit configured to output a video signal to a data output line in a time division. manner in each horizontal scanning period, and a connection switching circuit including a connection control transistor configured to control an electrical connection state between each of the video signal lines and the data output line corresponding thereto, the data output line corresponding to each video signal line group obtained by grouping the plurality of video signal lines with K video signal lines set as one group, where K is an integer of two or more, the connection switching circuit configured to switch a connection destination of the data output line corresponding to each of the video signal line groups among the K video signal lines configuring each of the video signal line groups, the method comprising:
a preliminary charging step of switching the connection destination of the data output line by the connection switching circuit so that, in case where the connection control transistor is of an n-channel a preliminary charging voltage is applied to the video signal line connected to the pixel formation portions to be subjected to data writing of a positive polarity and the video signal outputted from the video signal line drive circuit is applied to the video signal line connected to the pixel formation portions to be subjected to the data writing of a negative polarity, and in a case where the connection control transistor is of a p-channel type, the preliminary charging voltage is applied to the video signal line connected to the pixel formation portions to be subjected to the data writing of the negative polarity and the video signal outputted from the video signal line drive circuit is applied to the video signal line connected to the pixel formation portions to be subjected to the data writing of the positive polarity; and
a primary charging step of switching the connection destination of the data output line by the connection switching circuit so that, in the case where the connection control transistor is the n-channel type, the video signal outputted from the video signal line drive circuit is applied to the video signal line connected to the pixel formation portions to be subjected to the data writing of the positive polarity, and in the case where the connection control transistor is of the p-channel type, the video signal outputted from the video signal line drive circuit is applied to the video signal line connected to the pixel formation portions to be subjected to the data writing of the negative polarity.