# US 2019/0318461 A1 · Histogram Statistics Circuit and Multimedia Processing System

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0318461 A1
- Document ID: US20190318461A1
- Status: Published application
- Kind: A1
- Application number: 16/456,916
- Filed: 2019-06-28
- Published: 2019-10-17
- Earliest claimed: 2016-12-30
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: Yunbi Chen; Kai Hu
- Web page: https://patentgrep.com/patent/US20190318461A1

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06T 5/40: using histogram techniques
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/321: {Program or instruction counter, e.g. incrementing}
- G06F 17/18: for evaluating statistical data {, e.g. average values, frequency distributions, probability functions, regression analysis (forecasting specially adapted for a specific administrative, business or logistic context G06Q10/04)}
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments of the present invention disclose a histogram statistics circuit and a multimedia processing system. The multimedia processing system includes: a memory, a histogram statistics circuit, and a processor. The memory is configured to store multimedia data. The histogram statistics circuit is configured to: obtain the multimedia data from the memory, and perform histogram statistics on the multimedia data, to generate a statistical result. The processor is configured to process the multimedia data based on the statistical result and a histogram application algorithm. In the present invention, the histogram statistics circuit can complete calculation of a plurality of pixels in parallel, and the multimedia data is properly grouped to reduce some ineffective operations. Therefore, computing efficiency of the multimedia processing system is greatly improved, and a requirement on real-time quality in a scenario such as facial recognition can be met.

## Claims

### Claim 1

A histogram statistics circuit, wherein the histogram statistics circuit is coupled to a memory, the memory stores multimedia data, and the histogram statistics circuit comprises a counter cache, a controller, a parsing circuit, a matching-and-decoding circuit, and a count value updating circuit, wherein the controller is coupled to the counter cache, the parsing circuit, and the matching-and-decoding circuit, and the count value updating circuit is coupled between the counter cache and the matching-and-decoding circuit;
the counter cache is configured to cache Y groups of counters, wherein each group of counters comprises at least one counter and each counter corresponds to one current count value, and Y is a positive integer greater than 1;
the controller is configured to control the memory to group pixels in the multimedia data, to obtain M groups of data;
the parsing circuit is configured to perform the following step: obtaining an ith group of data from the M groups of data, and parsing each pixel value in the ith group of data, to determine X groups of counters that match the ith group of data in the Y groups of counters stored in the counter cache, wherein X is a positive integer and 1≤X≤Y; and the parsing circuit repeatedly performs the step until i=M, wherein i is a natural number whose starting value is I and is increased by 1 in each iterative process;
the controller is further configured to control, based on the X groups of counters determined by the parsing circuit, the matching-and-decoding circuit to match the ith group of data with each of the X groups of counters in X clock cycles;
the matching-and-decoding circuit is configured to perform the following step: in a jth clock cycle, matching each pixel in the ith group of data with a jth group of counters in the X groups of counters, and instructing, based on a matching result, the count value updating circuit to update a count value of the jth group of counters; and the matching-and-decoding circuit repeatedly performs the step until j=X, wherein j is a natural number whose starting value is 1 and is increased by 1 in each iterative process; and
the count value updating circuit is configured to: read a current count value of the jth group of counters from the counter cache in the jth clock cycle, update the current count value of the jth group of counters based on the matching result indicated by the matching-and-decoding circuit, to obtain an updated count value of the jth group of counters, and write back the updated count value of the jth group of counters into the jth group of counters in the counter cache.

### Claim 2 (depends on 1)

The histogram statistics circuit according to claim 1, wherein the controller is configured to control the memory to group the multimedia data by rows, by columns, or by matrices, to obtain the M groups of data.

### Claim 3 (depends on 1)

The histogram statistics circuit according to claim 1, wherein the parsing circuit is configured to: parse the value of each pixel in the ith group of data, determine a first value range of each pixel in the ith group of data, and determine, based on the first value range, the X groups of counters that match the ith group of data.

### Claim 4 (depends on 3)

The histogram statistics circuit according to claim 3, wherein the parsing circuit is configured to: parse the value of each pixel in the ith group of data, to obtain a maximum pixel value and a minimum pixel value in the ith group of data, and determine the first value range of the ith group of data based on the maximum pixel value and the minimum pixel value.

### Claim 5 (depends on 3)

The histogram statistics circuit according to claim 3, wherein the parsing circuit is configured to: when Y=2K, determine, based on K high-order bits of each pixel in the ith group of data, the X groups of counters that match the ith group of data, wherein K is a positive integer and 1≤K≤8,

### Claim 6 (depends on 1)

The histogram statistics circuit according to claim 1, wherein the parsing circuit is further configured to: generate indication information, and send the indication information to the controller, to indicate the X groups of counters.

### Claim 7 (depends on 1)

The histogram statistics circuit according to claim 1, wherein the matching-and-decoding circuit is configured to: in the jth clock cycle, match each pixel in the ith group of data with the jth group of counters and
when any pixel in the ith group of data matches a first counter in the jth group of counters, instruct the count value updating circuit to update a current count value of the first counter.

### Claim 8 (depends on 7)

The histogram statistics circuit according to claim 7, wherein the matching-and-decoding circuit is further configured to: when no pixel in the ith group of data matches any counter in the jth group of counters, instruct the count value updating circuit to maintain the current count value of the jth group of counters unchanged.

### Claim 9 (depends on 1)

The histogram statistics circuit according to claim 1, wherein the count value updating circuit specifically comprises at least one adder, a quantity of the at least one adder is equal to a quantity of counters in the jth group of counters, the at least one adder and the counters in the jth group of counters are in a one-to-one correspondence, any adder is configured to read a current count value of a second counter corresponding to the any adder from the counter cache, and when the matching-and-decoding circuit indicates that any pixel in the ith group of data matches the second counter, the any adder adds 1 to the current count value of the second counter to obtain an updated count value of the second counter, and writes back the updated count value of the second counter into the second counter in the counter cache to replace the current count value of the second counter.

### Claim 10 (depends on 1)

The histogram statistics circuit according to claim 1, wherein when a current count value of any counter stored in the counter cache is stored in two parts: a high-order part and a low-order part, the low-order part comprises low-order bits and an overflow bit that is set prior to the low-order bits, and when adders configured to update the current count value of the any counter comprise a first adder and a second adder, bit widths of high-order bits and the low-order bits satisfy the following formulas:
{
W
CNT
>
W
data
W
CNT


_


LOW
≥
W
group
W
CNT
=
W
CNT


_


LOW
+
W
CNT


_


HIGH
,
wherein
WCNT indicates a total bit width of the current count value of the any counter, Wdata indicates a bit width of a quantity of pixels in the multimedia data, WCNT_LOW indicates the bit width of the low-order bits, WCNT_HIGH indicates the bit width of the high-order bits, and Wgroup indicates a bit width of a quantity of pixels in any group of data in the M groups of data;
the first adder is configured to: when the matching-and-decoding circuit indicates that any pixel in the ith group of data matches the any counter, read the low-order bits of the current count value of the any counter and add 1, and write hack an updated value of the low-order bits into the low-order part of the any counter in the counter cache; and
the controller is further configured to:
detect the overflow bit, and when a value of the overflow bit is 1, read the high-order bits of the current count value of the any counter into the second adder, so that the second adder adds 1 and writes back an updated value of the high-order bits into the high-order part of the any counter in the counter cache.

### Claim 11

A multimedia processing system, comprising a memory, a histogram statistics circuit, and a processor, wherein
the memory is configured to store multimedia data;
the histogram statistics circuit is configured to: obtain the multimedia data from the memory, and perform histogram statistics on the multimedia data, to generate a statistical result; and
the processor is configured to process the multimedia data based on the statistical result and a histogram application algorithm; wherein
the histogram statistics circuit comprises a counter cache, a controller, a parsing circuit, a matching-and-decoding circuit, and a count value updating circuit, wherein the controller is coupled to the counter cache, the parsing circuit, and the matching-and-decoding circuit, and the count value updating circuit is coupled between the counter cache and the matching-and-decoding circuit;
the counter cache is configured to cache Y groups of counters, wherein each group of counters comprises at least one counter and each counter corresponds to one current count value, and Y is a positive integer greater than 1;
the controller is configured to control the memory to group pixels in the multimedia data, to obtain M groups of data;
the parsing circuit is configured to perform the following step: obtaining an ith group of data from the M groups of data, and parsing each pixel value in the ith group of data, to determine X groups of counters that match the ith group of data in the Y groups of counters stored in the counter cache, wherein X is a positive integer and 1≤X≤Y; and the parsing circuit repeatedly performs the step until i=M, wherein i is a natural number whose starting value is 1 and is increased by 1 in each iterative process;
the controller is further configured to control, based on the X groups of counters determined by the parsing circuit, the matching-and-decoding circuit to match the ith group of data with each of the X groups of counters in X clock cycles;
the matching-and-decoding circuit is configured to perform the following step: in a jth clock cycle, matching each pixel in the ith group of data with a jth group of counters in the X groups of counters, and instructing, based on a matching result, the count value updating circuit to update a count value of the jth group of counters; and the matching-and-decoding circuit repeatedly performs the step until j=X, wherein j is a natural number whose starting value is I and is increased by 1 in each iterative process; and
the count value updating circuit is configured to: read a current count value of the jth group of counters from the counter cache in the jth clock cycle, update the current count value of the jth group of counters based on the matching result indicated by the matching-and-decoding circuit, to obtain an updated count value of the jth group of counters, and write back the updated count value of the jth group of counters into the jth group of counters in the counter cache.

### Claim 12 (depends on 11)

The multimedia processing system according to claim 11, wherein the histogram application algorithm comprises: any one of a histogram equalization algorithm, an important image feature histogram of oriented gradients (HOG) algorithm, a mean shift algorithm, or a continuously adaptive mean shift algorithm.

### Claim 13 (depends on 11)

The multimedia processing system according to claim 11, wherein the multimedia processing system further comprises an obtaining apparatus, configured to: obtain the multimedia data, and write the multimedia data into the memory.

### Claim 14 (depends on 11)

The multimedia processing system according to claim 11, wherein the processor and the histogram statistics circuit are integrated into a same integrated circuit (IC).