# US 2019/0318232 A1 · Scalable Integrated Circuit with Synaptic Electronics and CMOS integrated Memristors

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- Number: US 2019/0318232 A1
- Document ID: US20190318232A1
- Status: Published application
- Kind: A1
- Application number: 16/447,210
- Filed: 2019-06-20
- Published: 2019-10-17
- Earliest claimed: 2013-10-14
- Assignees: HRL Laboratories, LLC
- Applicants: HRL Laboratories, LLC
- Inventors: Jose Cruz-Albrecht; Timothy Derosier; Narayan Srinivasa
- Web page: https://patentgrep.com/patent/US20190318232A1

## CPC

- G06N 3/049: Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
- G06N 3/063: using electronic means
- G06N 3/0499: Feedforward networks
- G06N 3/065: Analogue means
- G06N 3/08: Learning methods
- G06N 3/082: modifying the architecture, e.g. adding, deleting or silencing nodes or connections
- G06N 3/088: Non-supervised learning, e.g. competitive learning
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A reconfigurable neural circuit includes an array of processing nodes. Each processing node includes a single physical neuron circuit having only one input and an output, a single physical synapse circuit having a presynaptic input, and a single physical output coupled to the input of the neuron circuit, a weight memory for storing N synaptic conductance value or weights having an output coupled to the single physical synapse circuit, a single physical spike timing dependent plasticity (STDP) circuit having an output coupled to the weight memory, a first input coupled to the output of the neuron circuit, and a second input coupled to the presynaptic input, and interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit. The synapse circuit and the STDP circuit are each time multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

## Claims

### Claim 1

A reconfigurable neural circuit comprising:
an array comprising a plurality of processing nodes;
wherein each processing node comprises:
a single physical neuron circuit, the single physical neuron circuit having only one input and having an output;
a single physical synapse circuit, the single physical synapse circuit having a presynaptic input, and the single physical synapse circuit having a single physical output coupled to the only one input of the single physical neuron circuit;
a weight memory for storing N synaptic conductance value or weights, the weight memory having an output coupled to the single physical synapse circuit, wherein N is an integer greater than 1;
a single physical spike timing dependent plasticity (STDP) circuit, the single physical STDP circuit having an output coupled to an input of the weight memory, a first input coupled to the output of the single physical neuron circuit, and a second input coupled to the presynaptic input; and
interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit;
wherein the only one input of the single physical neuron circuit is only connected to the output of the single physical synapse circuit;
wherein the single physical synapse circuit is time multiplexed to implement N virtual synapse circuits; and
wherein the single physical STDP circuit is time multiplexed to implement N virtual STDP circuits; and
wherein the interconnect circuitry in each respective processing node in the array is coupled to the interconnect circuitry in each other processing node in the array.

### Claim 2 (depends on 1)

The reconfigurable neural circuit of claim 1:
wherein each processing node is adapted to read a respective one of the N synaptic conductance values or weights from the weight memory for each respective time period of N time periods and wherein each respective one of the N synaptic conductance values or weights coupled to the single physical synapse circuit during a respective time period of the N time periods causes the single physical synapse circuit to operate as a respective virtual synapse according to the coupled conductance value or weight during the respective time period; and
wherein each processing node is adapted to update the respective synaptic conductance value or weight read from the weight memory by writing the weight memory in the respective time period according to the output of the single physical spike timing dependent plasticity circuit during the respective time period.

### Claim 3 (depends on 1)

The reconfigurable neural circuit of claim 1 wherein:
the neuron circuit comprises an integrate and fire circuit.

### Claim 4 (depends on 1)

The reconfigurable neural circuit of claim 1 wherein:
the weight memory comprises a memristor memory, flip flops, a static random access memory or a digital memory.

### Claim 5 (depends on 1)

The reconfigurable neural circuit of claim 1:
wherein the interconnect circuitry in each processing node is coupled to the presynaptic input in each other processing node and coupled to the output of the single physical neuron circuit in each other processing node.

### Claim 6 (depends on 1)

The reconfigurable neural circuit of claim 1 wherein:
the interconnect circuitry comprises a plurality of switches for changing the interconnections to and from a respective processing node and other processing nodes in the array.

### Claim 7 (depends on 6)

The reconfigurable neural circuit of claim 6 wherein:
the plurality of switches comprise a plurality of uni-directional and bi-directional switches.

### Claim 8 (depends on 1)

The reconfigurable neural circuit of claim 1 wherein:
the single physical STDP circuit comprises a biologically inspired spike timing dependent plasticity (STDP) learning rule.

### Claim 9 (depends on 1)

The reconfigurable neural circuit of claim 1 wherein:
the array comprises a two dimensional array of processing nodes.

### Claim 10 (depends on 1)

The reconfigurable neural circuit of claim 1 wherein each processing node further comprises:
a connectivity memory;
wherein the interconnect circuitry in each processing node comprises a plurality of switches;
wherein the connectivity memory stores a plurality of interconnect circuitry routing controls for each respective switch of the plurality of switches; and
wherein the plurality of interconnect circuitry routing controls for a respective switch of the plurality of switches is configured to control the respective switch for each respective time period of N time periods.

### Claim 11 (depends on 10)

The reconfigurable neural circuit of claim 10:
wherein the interconnect circuitry routing controls stored in the connectivity memory in each processing node determine whether the output of the single physical neuron circuit in a respective processing node is connected to a respective presynaptic input in another processing node.

### Claim 12 (depends on 10)

The reconfigurable neural circuit of claim 10:
wherein the interconnect circuitry in a respective processing node provides connections between the single physical neuron circuit, the single physical synapse circuit, and the single physical STDP circuit in the respective processing node.

### Claim 13 (depends on 10)

The reconfigurable neural circuit of claim 10:
wherein the plurality of interconnect circuitry routing controls stored in the connectivity memory in a respective processing node is programmed independently for each respective processing node in the array.

### Claim 14 (depends on 10)

The reconfigurable neural circuit of claim 10:
wherein the connectivity memory has a column corresponding to each respective switch in a processing node;
wherein each column has N rows corresponding to the N time periods; and
wherein the interconnect circuitry routing controls in a column for a respective switch comprise N controls for the respective switch, wherein each of the N controls is ON or OFF.

### Claim 15 (depends on 1)

The reconfigurable neural circuit of claim 1:
wherein during operation, time is divided into synaptic time multiplexing cycles;
wherein each cycle comprises N time slots; and
wherein during each of the N time slots the weight memory outputs a respective one of the N synaptic conductance value or weights, the single physical synapse circuit implements a respective one of the N virtual synapse circuits and outputs an output of the respective one of the N virtual synapse circuits to the single physical neuron circuit, and the single physical STDP circuit implements a respective one of the N virtual STDP circuits based on the output of the single physical neuron circuit during the time slot and the presynaptic input during the time slot, and update the respective one of the N synaptic conductance value or weights during the time slot.

### Claim 16 (depends on 15)

The reconfigurable neural circuit of claim 15:
wherein each processing node has a connectivity memory for controlling the interconnect circuitry in the processing node; and
wherein during each time slot the interconnect circuitry in a respective processing node is configured according to controls read from the connectivity memory in the respective processing node.

### Claim 17

A method for providing a reconfigurable neural circuit comprising:
providing an array comprising a plurality of processing nodes;
wherein each processing node comprises:
a single physical neuron circuit, the single physical neuron circuit having only one input and having an output;
a single physical synapse circuit, the single physical synapse circuit having a presynaptic input, and the single physical synapse circuit having a single physical output coupled to the only one input of the single physical neuron circuit;
a weight memory for storing N synaptic conductance value or weights, the weight memory having an output coupled to the single physical synapse circuit, wherein N is an integer greater than 1;
a single physical spike timing dependent plasticity (STDP) circuit, the single physical STDP circuit having an output coupled to an input of the weight memory, a first input coupled to the output of the single physical neuron circuit, and a second input coupled to the presynaptic input; and
interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit;
wherein the only one input of the single physical neuron circuit is only connected to the output of the single physical synapse circuit;
wherein the single physical synapse circuit is time multiplexed to implement N virtual synapse circuits; and
wherein the single physical STDP circuit is time multiplexed to implement N virtual STDP circuits; and
wherein the interconnect circuitry in each respective processing node in the array is coupled to the interconnect circuitry in each other processing node in the array.

### Claim 18 (depends on 17)

The method of claim 17:
reading a respective one of the N synaptic conductance values or weights from the weight memory for each respective time period of N time periods and wherein each respective one of the N synaptic conductance values or weights coupled to the single physical synapse circuit during a respective time period of the N time periods causes the single physical synapse circuit to operate as a respective virtual synapse according to the coupled conductance value or weight during the respective time period; and
updating the respective synaptic conductance value or weight read from the weight memory by writing the weight memory in the respective time period according to the output of the single physical spike timing dependent plasticity circuit during the respective time period.

### Claim 19 (depends on 17)

The method of claim 17 wherein:
the neuron circuit comprises an integrate and fire circuit.

### Claim 20 (depends on 17)

The method of claim 17 wherein:
the weight memory comprises a memristor memory, flip flops, a static random access memory or a digital memory.

### Claim 21 (depends on 17)

The method of claim 17:
wherein the interconnect circuitry in each processing node is coupled to the presynaptic input in each other processing node and coupled to the output of the single physical neuron circuit in each other processing node.

### Claim 22 (depends on 17)

The method of claim 17 wherein:
the interconnect circuitry comprises a plurality of switches for changing the interconnections to and from a respective processing node and other processing nodes in the array.

### Claim 23 (depends on 22)

The method of claim 22 wherein:
the plurality of switches comprise a plurality of uni-directional and bi-directional switches.

### Claim 24 (depends on 17)

The method of claim 17 wherein:
the STDP circuit comprises a biologically inspired spike timing dependent plasticity (STDP) learning rule.

### Claim 25 (depends on 17)

The method of claim 17 wherein:
providing the array comprises providing a two dimensional array of processing nodes.

### Claim 26 (depends on 17)

The method of claim 17:
wherein each processing node further comprises:
a connectivity memory;
wherein the interconnect circuitry in each processing node comprises a plurality of switches; and
storing in the connectivity memory a plurality of interconnect circuitry routing controls for each respective switch of the plurality of switches; and
configuring the plurality of interconnect circuitry routing controls for a respective switch of the plurality of switches to control the respective switch for each respective time period of N time periods.

### Claim 27 (depends on 26)

The method of claim 26:
wherein the interconnect circuitry routing controls stored in the connectivity memory in each processing node determine whether the output of the single physical neuron circuit in a respective processing node is connected to a respective presynaptic input in another processing node.

### Claim 28 (depends on 26)

The method of claim 26:
wherein the interconnect circuitry in a respective processing node provides connections between the single physical neuron circuit, the single physical synapse circuit, and the single physical STDP circuit in the respective processing node.

### Claim 29 (depends on 26)

The method of claim 26 further comprising:
programming the plurality of interconnect circuitry routing controls stored in the connectivity memory in each respective processing node;
wherein the programming is independent for each respective processing node in the array.

### Claim 30 (depends on 26)

The method of claim 26:
wherein the connectivity memory has a column corresponding to each respective switch in a processing node;
wherein each column has N rows corresponding to the N time periods; and
wherein the interconnect circuitry routing controls in a column for a respective switch comprise N controls for the respective switch, wherein each of the N controls is ON or OFF.

### Claim 31 (depends on 17)

The method of claim 17:
wherein during operation, time is divided into synaptic time multiplexing cycles;
wherein each cycle comprises N time slots; and
wherein during each of the N time slots the weight memory outputs a respective one of the N synaptic conductance value or weights, the single physical synapse circuit implements a respective one of the N virtual synapse circuits and outputs an output of the respective one of the N virtual synapse circuits to the single physical neuron circuit, and the single physical STDP circuit implements a respective one of the N virtual STDP circuits based on the output of the single physical neuron circuit during the time slot and the presynaptic input during the time slot, and update the respective one of the N synaptic conductance value or weights during the time slot.

### Claim 32 (depends on 31)

The method of claim 31:
wherein each processing node has a connectivity memory for controlling the interconnect circuitry in the processing node; and
wherein during each time slot the interconnect circuitry in a respective processing node is configured according to controls read from the connectivity memory in the respective processing node.