# US 2019/0318130 A1 · Countermeasures against hardware side-channel attacks on cryptographic operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0318130 A1 - Document ID: US20190318130A1 - Status: Published application - Kind: A1 - Application number: 16/456,308 - Filed: 2019-06-28 - Published: 2019-10-17 - Earliest claimed: 2019-06-28 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Santosh Ghosh; Debayan Das; Carlos Tokunaga; Avinash L. Varna; Joseph Friel - Web page: https://patentgrep.com/patent/US20190318130A1 ## CPC - G06F 21/72: in cryptographic circuits - G06F 21/123: {by using dedicated hardware, e.g. dongles, smart cards, cryptographic processors, global positioning systems [GPS] devices} - G06F 21/64: Protecting data integrity, e.g. using checksums, certificates or signatures - G06F 21/755: {with measures against power attack} - H04L 9/003: {for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores. ## Claims ### Claim 1 An apparatus comprising: a plurality of crypto cores; and a current source including a plurality of current source blocks, the plurality of current source blocks including a respective current source block associated with each of the plurality of crypto cores; and wherein the plurality of current sources blocks are switchable to switch on a current source block associated with each active core of the plurality of crypto cores and to switch off a current source block associated with each inactive core of the plurality of crypto cores. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising a plurality of switches, wherein the plurality of switches includes a respective switch associated with each of the plurality of crypto cores and a respective switch associated with each of the plurality of current source blocks. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the plurality of switches are controlled by digital control signals. ### Claim 4 (depends on 1) The apparatus of claim 1, further comprising a capacitor, the capacitor being connected across the plurality of crypto cores. ### Claim 5 (depends on 4) The apparatus of claim 4, further comprising a bypass path, the bypass path being connected across the plurality of crypto cores. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the bypass path includes one of a PMOS (P-Type Metal-Oxide Semiconductor) transistor, an NMOS (N-Type Metal-Oxide Semiconductor) transistor, or Op-amp (Operational Amplifier) based techniques. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein each current source block of the current source includes one or more current source slices. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein a number of current source slices for each current source block is determined based on an average current consumption for a crypto core associated with the current source block. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the apparatus is an integrated circuit (IC), the IC including a power pin that is coupled with the current source. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein power connections to the crypto cores are isolated within the IC. ### Claim 11 A system comprising: one or more processors; a memory for storage of data; a crypto block including a plurality of crypto cores; and an active SNR (Signal to Noise Ratio) reduction circuit coupled with the crypto block, the active SNR reduction circuit including: a current source including a plurality of current source blocks, the plurality of current source blocks including a respective current source block associated with each of the plurality of crypto cores; and wherein the plurality of current source blocks are switchable to switch on a current source block associated with each active core of the plurality of crypto cores and to switch off a current source block associated with each inactive core of the plurality of crypto cores. ### Claim 12 (depends on 11) The system of claim 11, wherein the active SNR reduction circuit further includes a plurality of switches, wherein the plurality of switches includes a respective switch associated with each of the plurality of crypto cores and a respective switch associated with each of the plurality of current source blocks. ### Claim 13 (depends on 12) The system of claim 12, wherein the plurality of switches are controlled by digital control signals. ### Claim 14 (depends on 11) The system of claim 11, wherein the active SNR reduction circuit further includes a capacitor, the capacitor being connected across the plurality of crypto cores. ### Claim 15 (depends on 14) The system of claim 14, wherein the active SNR reduction circuit further includes a bypass path, the bypass path being connected across the plurality of crypto cores. ### Claim 16 (depends on 15) The system of claim 15, wherein the bypass path includes one of a PMOS (P-Type Metal-Oxide Semiconductor) transistor, an NMOS (N-Type Metal-Oxide Semiconductor) transistor, or Op-amp (Operational Amplifier) based techniques. ### Claim 17 (depends on 11) The system of claim 11, wherein each current source block of the current source includes one or more current source slices. ### Claim 18 (depends on 17) The system of claim 17, wherein a number of current source slices for each current source block is determined based on an average current consumption for a crypto core associated with the current source block. ### Claim 19 (depends on 11) The system of claim 11, further comprising an integrated circuit (IC), the integrated circuit including the active SNR reduction circuit and the crypto block. ### Claim 20 (depends on 19) The system of claim 19, wherein the IC includes a power pin that is coupled with the current source, and wherein power connections to the crypto block are isolated within the IC. ### Claim 21 One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising: commencing operation of a system, the system including a crypto block including a plurality of crypto cores and an active SNR (Signal to Noise Ratio) reduction circuit coupled with the crypto block; and upon determining that a first crypto core of the plurality of crypto cores is to be turned on or off, switching a first current source block of a plurality of current source blocks of the active SNR reduction circuit, the first current source block to be switched on if the first crypto core is to be turned on and the first current source block to be switched off if the first crypto core is to be turned off. ### Claim 22 (depends on 21) The one or more storage mediums of claim 21, wherein the active SNR reduction circuit further includes a plurality of switches, and wherein switching the first current source block on or off includes switching a respective switch of the plurality of switches associated with the first crypto core and switching a respective switch of the plurality of switches associated with the first current source block. ### Claim 23 (depends on 21) The one or more storage mediums of claim 21, wherein the active SNR reduction circuit further includes a capacitor, the capacitor being connected across the plurality of crypto cores. ### Claim 24 (depends on 21) The one or more storage mediums of claim 21, wherein the active SNR reduction circuit further includes a bypass path, the bypass path being connected across the plurality of crypto cores.