# US 2019/0318097 A1 · Standardized Interface for Intellectual Property Blocks

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- Number: US 2019/0318097 A1
- Document ID: US20190318097A1
- Status: Published application
- Kind: A1
- Application number: 16/457,184
- Filed: 2019-06-28
- Published: 2019-10-17
- Earliest claimed: 2019-06-28
- Assignees: Intel Corporation
- Inventors: Aditya Katragada; Prashant Dewan; Karunakara Kotary; Vinupama Godavarthi; Kumar Dwarakanath; Alex Izbinsky; Purushottam Goel
- Web page: https://patentgrep.com/patent/US20190318097A1

## CPC

- G06F 21/57: Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F 21/572: {Secure firmware programming, e.g. of basic input output system [BIOS]}
- G06F 9/445: Program loading or initiating (bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57)
- G06F 21/121: {Restricting unauthorised execution of programs}
- G06F 21/72: in cryptographic circuits
- G06F 2221/033: Test or assess software
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

There is disclosed in one example, a system-on-a-chip (SoC), including: a processor core; a fabric; an intellectual property (IP) block communicatively coupled to the processor core via the fabric, the IP block having a microcontroller configured to provide a microcontroller architecture; a firmware load interface configured to provide a standardized hardware interface to the microcontroller architecture, wherein the standardized hardware interface provides an architecture-agnostic mechanism to securely load a firmware to the intellectual property block; and logic to provide a loader to load a firmware to the IP block via the firmware load interface.

## Claims

### Claim 1

A system-on-a-chip (SoC), comprising:
a processor core;
a fabric;
a first intellectual property (IP) block communicatively coupled to the processor core via the fabric, the first IP block having a first microcontroller configured to provide a first microcontroller architecture;
a first firmware load interface configured to provide a standardized hardware interface to the first microcontroller architecture, wherein the standardized hardware interface provides an architecture-agnostic mechanism to securely load a first firmware to the first intellectual property block; and
logic to provide a loader to load a firmware to the first IP block via the first firmware load interface.

### Claim 2 (depends on 1)

The SoC of claim 1, wherein the first firmware load interface is integrated into the first IP block.

### Claim 3 (depends on 1)

The SoC of claim 1, wherein the first firmware load interface is external to the first IP block.

### Claim 4 (depends on 1)

The SoC of claim 1, wherein the first firmware load interface is an IP block discrete from the first IP block.

### Claim 5 (depends on 1)

The SoC of claim 1, further comprising:
a second IP block having a second microcontroller, the second microcontroller having a second microcontroller architecture different from the first microcontroller architecture; and
a second firmware load interface to provide the standardized hardware interface to securely load a second firmware to the second IP block.

### Claim 6 (depends on 1)

The SoC of claim 1, wherein securely loading the first firmware comprises a single-stage loading.

### Claim 7 (depends on 1)

The SoC of claim 1, wherein securely loading the first firmware comprises a multi-stage loading.

### Claim 8 (depends on 7)

The SoC of claim 7, wherein the multi-stage loading comprises loading by multiple agents at different stages of operation.

### Claim 9 (depends on 1)

The SoC of claim 1, wherein the processor core comprises a set of registers to control the securely loading the firmware.

### Claim 10 (depends on 1)

The SoC of claim 1, further comprising a security engine to securely load the first firmware to the first IP block.

### Claim 11

An intellectual property (IP) block, comprising:
a microcontroller; and
a firmware dashboard, the firmware dashboard comprising:
an IP-facing interface comprising circuitry to interface internally with the IP block; and
a system-facing interface comprising circuitry to provide a standardized load interface for a firmware of the IP block.

### Claim 12 (depends on 11)

The IP block of claim 11, further comprising an internal cryptographic module configured to cryptographically verify the firmware.

### Claim 13 (depends on 11)

The IP block of claim 11, further comprising a read-only memory (ROM), wherein the IP-facing interface comprises instructions to populate the ROM with the firmware.

### Claim 14 (depends on 11)

The IP block of claim 11, wherein the IP block is configured to receive the address and size of an IP-block-addressable memory location of the system, the memory location to contain the firmware.

### Claim 15 (depends on 11)

The IP block of claim 11, wherein the IP block lacks an internal memory to hold the firmware, and wherein the IP block is configured to execute the firmware directly from an addressable location in main memory for the system.

### Claim 16

An integrated circuit, comprising:
a first interface configured to communicatively couple to an intellectual property (IP) block;
a second interface configured to communicatively couple to a system-on-a-chip (SoC); and
circuitry to provide bridge and wrapper functionality between the IP block and the SoC, wherein the bridge and wrapper functionality are to provide a standardized and architecture-agnostic load flow to load a firmware to the IP block, and to carry out the load flow in a manner specific to an architecture of the IP block.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein the load flow supports a firmware push model for the IP block.

### Claim 18 (depends on 16)

The integrated circuit of claim 16, wherein the load flow supports a firmware pull model for the IP block.

### Claim 19 (depends on 16)

The integrated circuit of claim 16, wherein the load flow supports an on-IP firmware verification security model.

### Claim 20 (depends on 16)

The integrated circuit of claim 16, wherein the load flow supports an off-IP firmware verification security model.