# US 2019/0318082 A1 · Techniques for control flow protection

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- Number: US 2019/0318082 A1
- Document ID: US20190318082A1
- Status: Published application
- Kind: A1
- Application number: 16/452,916
- Filed: 2019-06-26
- Published: 2019-10-17
- Earliest claimed: 2017-05-25
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: ABHISHEK BASAK; RAVI SAHITA; VEDVYAS SHANBHOGUE
- Web page: https://patentgrep.com/patent/US20190318082A1

## CPC

- G06F 21/52: during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow}
- G06F 12/06: Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence)
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1052: Security improvement
- G06F 2212/154: Networked environment
- G06F 2221/033: Test or assess software
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Various embodiments are generally directed to techniques for control flow protection with minimal performance overhead, such as by utilizing one or more micro-architectural optimizations to implement a shadow stack (SS) to verify a return address before returning from a function call, for instance. Some embodiments are particularly directed to a computing platform, such as an internet of things (IoT) platform, that overlaps or parallelizes one or more SS access operations with one or more data stack (DS) access operations.

## Claims

### Claim 1

An apparatus, comprising:
a processor; and
memory comprising instructions that when executed by the processor cause the processor to:
determine to evict a cache line from a cache memory comprising a first cache line and a second cache line;
preserve the first cache line in the cache memory based on determination of an association between the first cache line and a shadow stack; and
select the second cache line to evict from the cache memory based on determination of no association between the second cache line and the shadow stack.

### Claim 2 (depends on 1)

The apparatus of claim 1, the memory comprising instructions that when executed by the processor cause the processor to:
access a first entry of a page table to determine the association between the first cache line and the shadow stack, wherein the first entry of the page table corresponds to the first cache line; and
access a second entry of the page table to determine no association between the second cache line and the shadow stack, wherein the second entry of the page table corresponds to the second cache line.

### Claim 3 (depends on 2)

The apparatus of claim 2, the cache memory comprising a third cache line and the memory comprising instructions that when executed by the processor cause the processor to:
access a third entry of the page table to determine no association between the third cache line and the shadow stack, wherein the third entry of the page table corresponds to the third cache line;
evaluate the second cache line and the third cache line with a least recently used cache line replacement policy based on determination of no association between the second cache line and the shadow stack and determination of no association between the third cache line and the shadow stack; and
select the second cache line to evict from the cache memory based on the least recently used cache line replacement policy.

### Claim 4 (depends on 2)

The apparatus of claim 2, the memory comprising instructions that when executed by the processor cause the processor to:
analyze a bit in the first entry of the page table to determine the association between the first cache line and the shadow stack; and
analyze a bit in the second entry of the page table to determine no association between the second cache line and the shadow stack.

### Claim 5 (depends on 4)

The apparatus of claim 4, the cache memory comprising a third cache line, the page table comprising a third entry that corresponds to the third cache line, and the memory comprising instructions that when executed by the processor cause the processor to:
analyze a bit in the third entry of the page table to determine no association between the third cache line and the shadow stack;
evaluate the second cache line and the third cache line with a least recently used cache line replacement policy based on determination of no association between the second cache line and the shadow stack and determination of no association between the third cache line and the shadow stack; and
select the second cache line to evict from the cache memory based on the least recently used cache line replacement policy.

### Claim 6 (depends on 2)

The apparatus of claim 2, the first entry of the page table comprising a plurality of shadow stack pointers.

### Claim 7 (depends on 2)

The apparatus of claim 2, the first entry of the page table comprising a shadow stack pointer that identifies a predefined location on the shadow stack.

### Claim 8 (depends on 7)

The apparatus of claim 7, the predefined location on the shadow stack comprising the top of the shadow stack.

### Claim 9 (depends on 2)

The apparatus of claim 2, the first entry of the page table to identify a number of active entries in a shadow stack buffer.

### Claim 10 (depends on 1)

The apparatus of claim 1, the memory comprising instructions that when executed by the processor cause the processor to prevent modification to the first cache line based on determination of the association between the first cache line and the shadow stack.

### Claim 11 (depends on 1)

The apparatus of claim 1, the memory comprising instructions that when executed by the processor cause the processor to calculate a shadow stack memory address based on the first cache line and in response to a call instruction.

### Claim 12

At least one non-transitory computer-readable medium comprising a set of instructions that, in response to being executed by a processor circuit, cause the processor circuit to:
determine to evict a cache line from a cache memory comprising a first cache line and a second cache line;
preserve the first cache line in the cache memory based on determination of an association between the first cache line and a shadow stack; and
select the second cache line to evict from the cache memory based on determination of no association between the second cache line and the shadow stack.

### Claim 13 (depends on 12)

The at least one non-transitory computer-readable medium of claim 12, comprising instructions that, in response to being executed by the processor circuit, cause the processor circuit to:
access a first entry of a page table to determine the association between the first cache line and the shadow stack, wherein the first entry of the page table corresponds to the first cache line; and
access a second entry of the page table to determine no association between the second cache line and the shadow stack, wherein the second entry of the page table corresponds to the second cache line.

### Claim 14 (depends on 13)

The at least one non-transitory computer-readable medium of claim 13, comprising instructions that, in response to being executed by the processor circuit, cause the processor circuit to:
access a third entry of the page table to determine no association between a third cache line in the cache memory and the shadow stack, wherein the third cache line corresponds to the third entry of the page table;
evaluate the second cache line and the third cache line with a least recently used cache line replacement policy based on determination of no association between the second cache line and the shadow stack and determination of no association between the third cache line and the shadow stack; and
select the second cache line to evict from the cache memory based on the least recently used cache line replacement policy.

### Claim 15 (depends on 13)

The at least one non-transitory computer-readable medium of claim 13, comprising instructions that, in response to being executed by the processor circuit, cause the processor circuit to:
analyze a bit in the first entry of the page table to determine the association between the first cache line and the shadow stack; and
analyze a bit in the second entry of the page table to determine no association between the second cache line and the shadow stack.

### Claim 16 (depends on 15)

The at least one non-transitory computer-readable medium of claim 15, comprising instructions that, in response to being executed by the processor circuit, cause the processor circuit:
analyze a bit in a third entry of the page table to determine no association between a third cache line in the cache memory and the shadow stack, wherein the third cache line corresponds to the third entry of the page table;
evaluate the second cache line and the third cache line with a least recently used cache line replacement policy based on determination of no association between the second cache line and the shadow stack and determination of no association between the third cache line and the shadow stack; and
select the second cache line to evict from the cache memory based on the least recently used cache line replacement policy.

### Claim 17 (depends on 12)

The at least one non-transitory computer-readable medium of claim 12, comprising instructions that, in response to being executed by the processor circuit, cause the processor circuit to prevent modification to the first cache line based on determination of the association between the first cache line and the shadow stack.

### Claim 18 (depends on 12)

The at least one non-transitory computer-readable medium of claim 12, comprising instructions that, in response to being executed by the processor circuit, cause the processor circuit to calculate a shadow stack memory address based on the first cache line and in response to a call instruction.

### Claim 19

A computer-implemented method, comprising:
determining to evict a cache line from a cache memory comprising a first cache line and a second cache line;
preserving the first cache line in the cache memory based on determination of an association between the first cache line and a shadow stack; and
selecting the second cache line to evict from the cache memory based on determination of no association between the second cache line and the shadow stack.

### Claim 20 (depends on 19)

The computer-implemented method of claim 19, comprising:
accessing a first entry of a page table to determine the association between the first cache line and the shadow stack, wherein the first entry of the page table corresponds to the first cache line; and
accessing a second entry of the page table to determine no association between the second cache line and the shadow stack, wherein the second entry of the page table corresponds to the second cache line.

### Claim 21 (depends on 20)

The computer-implemented method of claim 20, comprising:
accessing a third entry of the page table to determine no association between a third cache line in the cache memory and the shadow stack, wherein the third cache line corresponds to the third entry of the page table;
evaluating the second cache line and the third cache line with a least recently used cache line replacement policy based on determination of no association between the second cache line and the shadow stack and determination of no association between the third cache line and the shadow stack; and
selecting the second cache line to evict from the cache memory based on the least recently used cache line replacement policy.

### Claim 22 (depends on 20)

The computer-implemented method of claim 20, comprising:
analyzing a bit in the first entry of the page table to determine the association between the first cache line and the shadow stack; and
analyzing a bit in the second entry of the page table to determine no association between the second cache line and the shadow stack.

### Claim 23 (depends on 22)

The computer-implemented method of claim 22, comprising:
analyzing a bit in a third entry of the page table to determine no association between a third cache line in the cache memory and the shadow stack, wherein the third cache line corresponds to the third entry of the page table;
evaluating the second cache line and the third cache line with a least recently used cache line replacement policy based on determination of no association between the second cache line and the shadow stack and determination of no association between the third cache line and the shadow stack; and
selecting the second cache line to evict from the cache memory based on the least recently used cache line replacement policy.

### Claim 24 (depends on 19)

The computer-implemented method of claim 19, comprising preventing modification to the first cache line based on determination of the association between the first cache line and the shadow stack.

### Claim 25 (depends on 19)

The computer-implemented method of claim 19, comprising calculating a shadow stack memory address based on the first cache line and in response to a call instruction.