# US 2019/0318058 A1 · High Performance Regularized Network-on-Chip Architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0318058 A1 - Document ID: US20190318058A1 - Status: Published application - Kind: A1 - Application number: 16/457,114 - Filed: 2019-06-28 - Published: 2019-10-17 - Earliest claimed: 2019-03-18 - Assignees: Intel Corporation - Inventors: Gregg William Baeckler; Martin Langhammer; Sergey Vladimirovich Gribok - Web page: https://patentgrep.com/patent/US20190318058A1 ## CPC - G06F 30/347: Physical level, e.g. placement or routing - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 2115/02: System on chip [SoC] design - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques for designing and implementing networks-on-chip (NoCs) are provided. For example, a computer-implemented method for programming a network-on-chip (NoC) onto an integrated circuit includes determining a first portion of a plurality of registers to potentially be included in a NoC design, determining routing information regarding datapaths between registers of the first portion of the plurality of registers, and determining an expected performance associated with the first portion of the plurality of registers. The method also includes determining whether the expected performance is within a threshold range, including the first portion of the plurality of registers and the datapaths in the NoC design after determining that the expected performance is within the threshold range, and generating instructions configured to cause circuitry corresponding to the NoC design to be implemented on the integrated circuit. ## Claims ### Claim 1 A computer-implemented method for programming a network-on-chip (NoC) onto an integrated circuit, the method comprising: determining a first portion of a plurality of registers to potentially be included in a NoC design; determining routing information regarding datapaths between registers of the first portion of the plurality of registers; determining an expected performance associated with the first portion of the plurality of registers; determining whether the expected performance is within a threshold range; including the first portion of the plurality of registers and the datapaths in the NoC design based on determining that the expected performance is within the threshold range; and generating instructions configured to cause circuitry corresponding to the NoC design to be implemented on the integrated circuit. ### Claim 2 (depends on 1) The computer-implemented method of claim 1, wherein the first portion of the plurality of registers are selected from a library comprising potential register locations specific to the integrated circuit. ### Claim 3 (depends on 2) The computer-implemented method of claim 2, wherein the datapaths are selected from a plurality of chip-specific datapaths included in the library. ### Claim 4 (depends on 1) The computer-implemented method of claim 1, comprising moving one or more locations of registers of the first portion of the plurality of registers, altering a portion of the datapaths, or both based on determining that the expected performance is not within the threshold range. ### Claim 5 (depends on 1) The computer-implemented method of claim 1, comprising: determining whether the first portion of the plurality of registers includes registers that are located in more than one clock sector; and based on upon determining that the first portion of the plurality of registers includes registers that are located in more than one clock sector, moving one or more registers of the first portion of the plurality of registers so that each register of the first portion of the plurality of registers is included in a single clock sector. ### Claim 6 (depends on 1) The computer-implemented method of claim 1, wherein the plurality of registers comprises: a second portion of registers configured to route data vertically away from a data source; and a third portion of registers disposed perpendicular to the second portion of registers and configured to route data horizontally away from the data source. The computer-implemented method of claim 1, comprising: determining whether any of the datapaths are routed through an impassable area of the integrated circuit; and after determining that at least one of the datapaths is routed through the impassable area, altering a portion of the datapaths to run around the impassable area. ### Claim 8 (depends on 7) The computer-implemented method of claim 7, comprising altering one or more locations of a second plurality of registers of the plurality of registers based on altering the portion of the datapaths to run around the impassable area. ### Claim 9 (depends on 1) The computer-implemented method of claim 1, comprising: receiving a program design associated with a function to be performed by the integrated circuit; and compiling, based on the NoC design, the program design to generate a hardware implementation on the integrated circuit for the function. ### Claim 10 (depends on 1) The computer-implemented method of claim 1, comprising receiving desired performance information regarding the NoC design; and determining the first portion of a plurality of registers and the routing information based on the desired performance information. ### Claim 11 (depends on 1) The computer-implemented method of claim 1, wherein the integrated circuit comprises a programmable logic device. ### Claim 12 A non-transitory computer-readable medium comprising instructions that, when executed, are configured to cause one or more processors to: receive data regarding an integrated circuit and data regarding performance characteristics for a network-on-chip (NoC) to be designed; select source points and endpoints for the NoC based on the data regarding the integrated circuit and the data regarding performance characteristics for the NoC; determine routes between the source points and the endpoints; determine whether an expected performance level associated with the routes is within a threshold range of a performance level defined by the performance characteristics; include the endpoints and the routes in the NoC; and generate instructions configured to cause circuitry corresponding to the NoC to be implemented on the integrated circuit. ### Claim 13 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions are configured to cause the processing circuitry to: include the endpoints in the NoC comprises setting the endpoints as source points; determine second endpoints for the NoC based on the endpoints; determine routes between the endpoints and the second endpoints; determine second routes between the endpoints and the second endpoints; and include the second endpoints and the second routes in the NoC. ### Claim 14 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions are configured to cause the one or more processors to: move the endpoints closer to the source points based on determining that the expected performance level is slower than a minimum speed defined by the threshold range; and move end endpoints farther from the source points based on determining that the expected performance level is faster than a maximum speed defined by the threshold range. ### Claim 15 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions are configured to cause the one or more processors to include the endpoints and the routes in the NoC based on determining that the expected performance level is within threshold range. ### Claim 16 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the instructions are configured to cause the one or more processors to select the routes from the data regarding the integrated circuit based on the data regarding performance characteristics for the NoC. ### Claim 17 (depends on 12) The non-transitory computer-readable medium of claim 12, wherein the endpoints correspond to a plurality of registers of the integrated circuit. ### Claim 18 An integrated circuit configured to: receive instructions regarding a NoC design; and implement circuitry corresponding to the NoC design, wherein the NoC design is determined by: determining a first portion of a plurality of registers to potentially be included in the NoC design; determining routing information regarding datapaths between registers of the first portion of the plurality of registers; determining an expected performance associated with the first portion of the plurality of registers; determining whether the expected performance is within a threshold range; and including the first portion of the plurality of registers and the datapaths in the NoC design after determining that the expected performance is within the threshold range. ### Claim 19 (depends on 18) The integrated circuit of claim 18, comprising a programmable logic device. ### Claim 20 (depends on 19) The integrated circuit of claim 19, wherein the programmable logic device comprises a field programmable gate array (FPGA).