# US 2019/0318057 A1 · Voltage drop assisted power-grid augmentation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0318057 A1 - Document ID: US20190318057A1 - Status: Published application - Kind: A1 - Application number: 16/382,129 - Filed: 2019-04-11 - Published: 2019-10-17 - Earliest claimed: 2018-04-13 - Assignees: Synopsys, Inc. - Applicants: Synopsys, Inc. - Inventors: Himanshu Sharma - Web page: https://patentgrep.com/patent/US20190318057A1 ## CPC - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 2111/04: Constraint-based CAD - G06F 2111/20: Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules - G06F 2113/04: Power grid distribution networks - G06F 2119/06: Power analysis or power optimisation - G06F 2119/12: Timing analysis or timing optimisation - Y02E 60/00: Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation - Y04S 40/20: Information technology specific aspects, e.g. CAD, simulation, modelling, system security - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION - Y04S: SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS ## Abstract A method for reducing voltage hot spots in a power grid for a circuit design is implemented on a computer system and includes the following steps. The computer system (e.g., an EDA tool) accesses the circuit design. The circuit design includes a power grid that distributes power throughout the circuit design. The computer system identifies spots in the power grid with excessive voltage drops. These will be referred to as hot spots. The power grid is augmented by adding local conductors at the hot spots. These local conductors provide additional electrical paths through the power grid at the hot spots. This in turn reduces the voltage drops at the hot spots. ## Claims ### Claim 1 A method implemented on a computer system, the computer system executing instructions to carry out a method for reducing voltage hot spots in a power grid for a circuit design, the method comprising: accessing a circuit design, the circuit design comprising a power grid that distributes power throughout the circuit design; identifying hot spots in the power grid with excessive voltage drops; and augmenting the power grid by adding local conductors at the hot spots, the local conductors providing additional electrical paths through the power grid at the hot spots, thereby reducing the voltage drops at the hot spots. ### Claim 2 (depends on 1) The computer-implemented method of claim 1 wherein identifying hot spots is based on at least one of voltage drops for a ground net of the power grid, voltage drops for a power net of the power grid, or voltage drops across cells in the circuit design. ### Claim 3 (depends on 1) The computer-implemented method of claim 1 further comprising: augmenting the power grid by also adding local conductors outside the hot spots, but where the power grid is more aggressively augmented at the hot spots than outside the hot spots. ### Claim 4 (depends on 1) The computer-implemented method of claim 1 wherein a design of the added local conductors is determined based in part on an effect of the local conductor on a resistance through the power grid. ### Claim 5 (depends on 1) The computer-implemented method of claim 1 wherein a design of the added local conductors is determined based in part on an effect of the local conductor on a yield of the circuit. ### Claim 6 (depends on 1) The computer-implemented method of claim 1 wherein a design of the added local conductors is determined based in part on an effect of the local conductor on a critical area for the circuit. ### Claim 7 (depends on 1) The computer-implemented method of claim 1 wherein a design of the added local conductors is determined based in part on an effect of the local conductor on a timing of signals through the circuit. ### Claim 8 (depends on 1) The computer-implemented method of claim 1 further comprising: identifying timing-critical nets, wherein a design of the added local conductors is determined based in part on a location of the timing-critical nets. ### Claim 9 (depends on 1) The computer-implemented method of claim 1 wherein the power grid before augmentation follows a regular pattern. ### Claim 10 (depends on 1) The computer-implemented method of claim 1 wherein the power grid and the local conductors are laid out on a Manhattan geometry, and the power grid before augmentation comprises a plurality of parallel primary distribution lines electrically connected to a plurality of secondary distribution lines that are perpendicular to the primary distribution lines. ### Claim 11 (depends on 10) The computer-implemented method of claim 10 wherein the local conductors include straps that extend some of the distribution lines. ### Claim 12 (depends on 11) The computer-implemented method of claim 11 wherein the local conductors further include shunts that electrically connect different distribution lines and/or straps. ### Claim 13 (depends on 11) The computer-implemented method of claim 11 wherein the local conductors further include shunts that electrically connect different distribution shunts and/or straps. ### Claim 14 (depends on 1) The computer-implemented method of claim 1 wherein the circuit design is for a 16 nm or smaller technology node. ### Claim 15 (depends on 1) The computer-implemented method of claim 1 wherein the circuit design is laid out using double patterning. ### Claim 16 A non-transitory computer-readable storage medium storing executable computer program instructions for reducing voltage hot spots in a power grid for a circuit design, the instructions executable by a computer system and causing the computer system to perform a method comprising: accessing a circuit design, the circuit design comprising a power grid that distributes power throughout the circuit design; identifying hot spots in the power grid with excessive voltage drops; and augmenting the power grid by adding local conductors at the hot spots, the local conductors providing additional electrical paths through the power grid at the hot spots, thereby reducing the voltage drops at the hot spots. ### Claim 17 An electronic design automation (EDA) system for reducing voltage hot spots in a power grid for a circuit design, comprising: a data store that stores a circuit design, the circuit design comprising a power grid that distributes power throughout the circuit design; and an EDA tool suite in communication with the data store, the EDA tool suite configured to: identify hot spots in the power grid with excessive voltage drops; and augment the power grid by adding local conductors at the hot spots, the local conductors providing additional electrical paths through the power grid at the hot spots, thereby reducing the voltage drops at the hot spots. ### Claim 18 (depends on 17) The EDA system of claim 17 wherein the EDA tool suite includes a place and route tool that identify the hot spots in the power grid. ### Claim 19 (depends on 18) The EDA system of claim 18 wherein the EDA tool suite includes a separate EDA tool that augments the power grid by adding local conductors both at the hot spots and outside the hot spots, but that augments the power grid more aggressively at the hot spots than outside the hot spots. ### Claim 20 (depends on 18) The EDA system of claim 18 wherein the EDA tool suite includes a timing analysis tool that determines timing of signals through the circuit, and the EDA tool suite adds local conductors based in part on an effect of the local conductor on the timing of signals through the circuit.