# US 2019/0317907 A1 · Memory module threading with staggered data transfers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0317907 A1 - Document ID: US20190317907A1 - Status: Published application - Kind: A1 - Application number: 16/365,528 - Filed: 2019-03-26 - Published: 2019-10-17 - Earliest claimed: 2012-08-10 - Assignees: Rambus Inc. - Applicants: Rambus Inc. - Inventors: Hongzhong Zheng; Frederick A. Ware - Web page: https://patentgrep.com/patent/US20190317907A1 ## CPC - G06F 13/1673: {using buffers} - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 13/1678: {using bus width} - G06F 13/4059: {where the synchronisation uses buffers, e.g. for speed matching between buses} - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4094: Bit-line management or control circuits - G06F 2209/486: Scheduler internals - G06F 2209/5018: Thread allocation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus. ## Claims ### Claim 1 (canceled) ### Claim 2 A memory module, comprising: a substrate; buffer circuitry disposed on the substrate, the buffer circuitry for coupling to a primary data bus having a primary data bus width, the primary data bus to route data of a primary data transfer continuous throughput; plural memory device groups coupled to the buffer circuitry via respective secondary data bus paths, each of the plural memory device groups having a continuous throughput smaller than the primary data transfer continuous throughput, each of the plural memory device groups responsive to a memory request to transfer data groups collectively forming a data thread, the plural memory device groups isolated from the primary data bus by the buffer circuitry; and wherein the buffer circuitry includes steering logic to stagger transfer of multiple data groups from a first data thread across the primary data bus, and to stagger transfer of multiple data groups from a second data thread across the primary data bus. ### Claim 3 (depends on 2) The memory module according to claim 2, wherein: the plural memory device groups collectively form at least one module rank; and wherein each of the plural memory device groups is configured as a module sub-rank. ### Claim 4 (depends on 2) The memory module according to claim 2, wherein: each of the plural memory device groups interfaces with the buffer circuitry via a dedicated secondary bus path. ### Claim 5 (depends on 2) The memory module according to claim 2, wherein: the plural memory device groups each comprise at least one dynamic random access memory (DRAM) integrated circuit (IC) chip. ### Claim 6 (depends on 2) The memory module according to claim 2, wherein: the steering logic distributes a first data group of the first data thread from a first secondary data bus and a second data group from a second secondary data bus to the primary data bus such that the data groups from each data thread are staggered spatially. ### Claim 7 (depends on 6) The memory module according to claim 6, wherein: the steering logic distributes the first data group of the first data thread across a first portion of the primary data bus width during a first time interval, and the second data group of the second data thread across a second portion of the primary data bus width during the first time interval. ### Claim 8 (depends on 2) The memory module according to claim 2, wherein: the steering logic distributes a first data group of the first data thread from a first secondary data bus and a second data group from a second secondary data bus to the primary data bus such that the data groups from each data thread are staggered temporally. ### Claim 9 (depends on 8) The memory module according to claim 8, wherein: the steering logic distributes the first data group of the first data thread across the entire primary data bus width during a first time interval, and interleaves the first data group with the second data group that is distributed across the entire primary data bus width during a second time interval. ### Claim 10 A memory, comprising: at least one memory module for coupling to a memory controller via a primary data bus; wherein the at least one memory module includes a substrate; buffer circuitry disposed on the substrate, the buffer circuitry including a primary interface for coupling to a primary data bus, the primary data bus to route data of a primary data transfer continuous throughput; plural memory device groups coupled to the buffer circuitry via respective secondary data bus paths, each of the plural memory device groups having a continuous throughput smaller than the primary data transfer continuous throughput, each of the plural memory device groups responsive to a memory request to transfer data groups collectively forming a data thread, the plural memory device groups isolated from the primary data bus by the buffer circuitry; and wherein the buffer circuitry includes steering logic to stagger transfer of multiple data groups from a first data thread across the primary data bus, and to stagger transfer of multiple data groups from a second data thread across the primary data bus. ### Claim 11 (depends on 10) The memory according to claim 10, wherein: the primary interface is configured to couple to the memory controller in a multi-drop manner. ### Claim 12 (depends on 10) The memory according to claim 10, wherein: the primary interface is configured to couple to the memory controller in a point-to-point manner. ### Claim 13 (depends on 10) The memory according to claim 10, wherein: the at least one memory module includes a first memory module partitioned to transfer the first and second data threads, and a second memory module configured substantially similar to the first memory module, and partitioned to transfer third and fourth data threads. ### Claim 14 (depends on 13) The method according to claim 13, wherein: the first, second, third and fourth data threads are transferred across respective portions of the primary data bus during a first time interval, such that respective data groups from each data thread are transmitted in a spatially non-contiguous manner. ### Claim 15 (depends on 13) The method according to claim 13, wherein: at least one data group from each of the first, second, third and fourth data threads are transferred across the entire primary data bus width during respective time intervals, and collectively interleaved together, such that data groups from each data thread are transmitted in a temporally non-contiguous manner. ### Claim 16 (depends on 10) The memory according to claim 10, wherein: the plural memory device groups each comprise at least one dynamic random access memory (DRAM) integrated circuit (IC) chip. ### Claim 17 A method of operating a memory module having a substrate, buffer circuitry disposed on the substrate for coupling to a primary data bus, the primary data bus to route data of a primary data transfer continuous throughput, the method comprising: receiving a memory request to transfer data groups from plural memory device groups, the data groups collectively forming a data thread: staggering transfer of multiple data groups from a first data thread across the primary data bus; and staggering transfer of multiple data groups from a second data thread across the primary data bus. ### Claim 18 (depends on 17) The method according to claim 17, wherein the staggering transfer of the multiple data groups from the first and second data threads comprises: spatially distributing at least one of the multiple data groups of the first data thread across a first portion of the primary data bus, and at least one of the data groups of the second data thread across a second portion of the primary data bus. ### Claim 19 (depends on 17) The method according to claim 17, wherein the staggering transfer of the multiple data groups from the first and second data threads comprises: temporally distributing at least one of the multiple data groups of the first data thread across the entire primary data bus width of the primary data bus during a first time interval, with at least one of the multiple data groups of the second data thread across the entire primary data bus width during a subsequent time interval to collectively form interleaved data. ### Claim 20 (depends on 17) The method according to claim 17, wherein the transferring of the at least one of the data groups from the first and second data threads comprises: transmitting along a dedicated portion of the primary data bus in a point-to-point manner. ### Claim 21 (depends on 17) The method according to claim 17, wherein the transferring of the at least one of the data groups from the first and second data threads comprises: transmitting along a full width of the primary data bus in a multi-drop manner.