# US 2019/0317855 A1 · Error-correcting code memory

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- Number: US 2019/0317855 A1
- Document ID: US20190317855A1
- Status: Published application
- Kind: A1
- Application number: 16/453,081
- Filed: 2019-06-26
- Published: 2019-10-17
- Earliest claimed: 2017-01-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Indu Prathapan; Prashanth Saraf; Desmond Pravin Martin Fernandes; Saket Jalan
- Web page: https://patentgrep.com/patent/US20190317855A1

## CPC

- G06F 11/1044: {with specific ECC/EDC distribution}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- G06F 11/108: {Parity data distribution in semiconductor storages, e.g. in SSD}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
- H03M 13/35: Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
- H03M 13/356: {Unequal error protection [UEP]}
- H03M 13/3776: {using a re-encoding step during the decoding process}
- G11C 2207/2263: Write conditionally, e.g. only if new data and old data differ
- G11C 2207/229: Timing of a write operation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

## Claims

### Claim 1

A memory controller comprising:
read-modify-write logic configured to:
receive a partial write data request that includes partial write data;
retrieve read data from a memory device, in response to the partial write data request; and
combine the read data and the partial write data to form combined data;
error-correcting code check and repair logic coupled to the read-modify-write logic and configured to:
generate a first error-correcting code for the read data; and
check the read data for an error based on the first error-correcting code; and
an error-correcting code generator coupled to the read-modify-write logic and configured to generate a second error-correcting code for the combined data such that the generation of the second error-correcting code and the check of the read data are performed concurrently.

### Claim 2 (depends on 1)

The memory controller of claim 1, wherein the combination of the read data and the partial write data and the check of the read data are performed concurrently.

### Claim 3 (depends on 1)

The memory controller of claim 1, wherein the error-correcting code check and repair logic is further configured to generate a data repair pattern for the read data.

### Claim 4 (depends on 3)

The memory controller of claim 3 further comprising write control logic configured to correct the combined data based on the data repair pattern.

### Claim 5 (depends on 4)

The memory controller of claim 4, wherein the write control logic is configured to correct the combined data based on the data repair pattern by applying an exclusive-OR function to the combined data and the data repair pattern to form corrected combined data.

### Claim 6 (depends on 4)

The memory controller of claim 4, wherein:
the error-correcting code check and repair logic is further configured to generate an error-correcting code repair pattern for the second error-correcting code; and
the write control logic is further configured to correct the second error-correcting code based on the error-correcting code repair pattern.

### Claim 7 (depends on 1)

The memory controller of claim 1 further comprising write control logic coupled to the read-modify-write logic and configured to:
correct the combined data and the second error-correcting code; and
store the corrected combined data and the corrected second error-correcting code in the memory device.

### Claim 8 (depends on 7)

The memory controller of claim 7, wherein the write control logic is further configured to:
store the combined data and the second error-correcting code in the memory device prior to correction; and
update the memory device with the corrected combined data and the corrected second error-correcting code after the correction.

### Claim 9 (depends on 1)

The memory controller of claim 1, wherein:
the error-correcting code check and repair logic is further configured to generate an error signal in response to the check of the read data for the error; and
the memory controller further comprises write control logic coupled to the read-modify-write logic that includes a multiplexer configured to select between the combined data and corrected combined data to store in the memory device based on the error signal.

### Claim 10

A method comprising:
receiving a write request that includes an address and a data set;
retrieving, from a memory device, read data stored at the address and a first error-correcting code associated with the read data;
checking accuracy of the read data using the first error-correcting code;
combining the data set and the read data to produce combined data; and
generating a second error-correcting code for the combined data concurrent with the checking of the accuracy of the read data.

### Claim 11 (depends on 10)

The method of claim 10, wherein the combining of the data set and the read data and the checking of the accuracy of the read data are performed concurrently.

### Claim 12 (depends on 10)

The method of claim 10 further comprising:
generating a data repair pattern for the read data based on the accuracy of the read data; and
applying the data repair pattern to the combined data to produce corrected combined data.

### Claim 13 (depends on 12)

The method of claim 12 further comprising:
storing the combined data in the memory device; and
subsequently storing the corrected combined data in the memory device.

### Claim 14 (depends on 10)

The method of claim 10 further comprising:
generating an error-correcting code repair pattern based on the accuracy of the read data; and
applying the error-correcting code repair pattern to the second error-correcting code to produce corrected second error-correcting code.

### Claim 15 (depends on 10)

The method of claim 10 further comprising:
generating an error signal based on the accuracy of the read data; and
in response to the error signal, correcting the combined data.

### Claim 16 (depends on 15)

The method of claim 15 further comprising asserting a stall signal in response to the error signal.

### Claim 17

A memory controller comprising:
read-modify-write logic to:
receive a partial write data request containing partial write data;
receive, from a memory device, read data and a first error-correcting code associated with the read data in response to the partial write data request; and
combine the partial write data and the read data to produce combined data; and
error-correcting code check and repair logic coupled to the read-modify-write logic and configured to check the read data for an error based on the first error-correcting code such that the check of the read data for the error and the combination of the partial write data and the read data is performed concurrently.

### Claim 18 (depends on 17)

The memory controller of claim 17, wherein:
the error-correcting code check and repair logic is further configured to generate a data repair pattern for the read data; and
the memory controller further comprises write control logic configured to correct the combined data based on the data repair pattern.

### Claim 19 (depends on 17)

The memory controller of claim 17 further comprising an error-correcting code generator coupled to the read-modify-write logic and configured to generate a second error-correcting code for the combined data.

### Claim 20 (depends on 19)

The memory controller of claim 19, wherein:
the error-correcting code check and repair logic is further configured to generate an error-correcting code repair pattern; and
the memory controller further comprises write control logic configured to correct the second error correcting code based on the error-correcting code repair pattern.