# US 2019/0317852 A1 · Efficient Content-Addressable Memory Lookup Result Integrity Checking and Correcting Operations Including for Protecting the Accuracy of Packet Processing Operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0317852 A1 - Document ID: US20190317852A1 - Status: Published application - Kind: A1 - Application number: 15/954,488 - Filed: 2018-04-16 - Published: 2019-10-17 - Earliest claimed: 2018-04-16 - Assignees: Cisco Technology, Inc., a corporation of California - Applicants: Cisco Technology, Inc. - Inventors: Doron Shoham - Web page: https://patentgrep.com/patent/US20190317852A1 ## CPC - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - H04L 45/745: Address table lookup; Address filtering - H04L 45/74591: {using content-addressable memories [CAM]} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract In one embodiment, content-addressable memory lookup result integrity checking and correcting operations are performed, such as, but not limited to protecting the accuracy of packet processing operations. A lookup operation is performed in the content-addressable memory entries based on a lookup word resulting in one or more match vectors. One or multiple result match vectors are produced, depending on whether each of the content-addressable memory entries and the lookup word have been partitioned into multiple portions. An error accuracy code (e.g., error detection, error correction) is acquired for each portion of the one or multiple portions based on a corresponding portion of the lookup word. An accurate result is generated by processing each of the result match vector(s) with their corresponding error accuracy code. When using multiple portions, the (possibly corrected) result match vectors are combined into a single accurate result match vector. ## Claims ### Claim 1 A method, comprising: performing a lookup operation in a plurality of content-addressable memory entries based on a lookup word resulting in one or more match vectors, with each of said match vectors including an entry match result for each of the plurality of content-addressable memory entries; and generating an accurate result match vector by hardware of a content-addressable memory lookup engine, with said generating including processing each particular match vector of said one or more match vectors with a particular error accuracy code corresponding to said particular match vector. ### Claim 2 (depends on 1) The method of claim 1, comprising: said hardware of the content-addressable memory lookup engine acquiring from memory, based the lookup word, said particular accuracy code for said each particular match vector. ### Claim 3 (depends on 2) The method of claim 2, wherein the corresponding error accuracy code is an error correction code (ECC); and wherein said processing each of the one or more match vectors with a corresponding error accuracy code results in error correcting of a bit in a particular match vector of said one or more match vectors. ### Claim 4 (depends on 3) The method of claim 3, wherein each of the plurality of content-addressable memory entries is a binary content-addressable memory entry. ### Claim 5 (depends on 4) The method of claim 4, comprising updating a particular entry of the plurality of content-addressable memory entries to store a vector; and updating a corresponding one error correction code stored in said memory based on a current value of the corresponding one error correction code XOR'd with a particular error correction code of the vector. ### Claim 6 (depends on 1) The method of claim 1, wherein the corresponding error accuracy code is an error correction code. ### Claim 7 (depends on 6) The method of claim 6, wherein said processing each of the one or more match vectors with a corresponding error accuracy code results in error correcting of a bit in a particular match vector of said one or more match vectors. ### Claim 8 (depends on 7) The method of claim 7, comprising: determining the lookup word based on a packet; and processing the packet based on processing information acquired based on a matching content-addressable memory entry of the plurality of content-addressable memory entries identified as matching in the accurate result match vector. ### Claim 9 (depends on 1) The method of claim 1, wherein the corresponding error accuracy code is an error detection code. ### Claim 10 (depends on 1) The method of claim 1, wherein said one or more match vectors comprise a plurality of portion match vectors; and wherein said performing the lookup operation includes producing the plurality of portion match vectors using a content-addressable memory matching operation in each of a plurality of entry portions of the plurality of content-addressable memory entries based on a corresponding portion of the lookup word; and wherein said processing each particular match vector of said one or more match vectors includes processing each specific portion match vector of the plurality of portion match vectors with a specific error accuracy code corresponding to said specific portion match vector to generate a specific accurate portion result vector of a plurality of specific accurate portion result vectors; and wherein generating the accurate result match vector includes combining each of the plurality of specific accurate portion result vectors. ### Claim 11 (depends on 10) The method of claim 10, comprising: said hardware of the content-addressable memory lookup engine acquiring from memory each of the plurality of specific accurate portion result vectors based on a corresponding portion of the lookup word. ### Claim 12 (depends on 11) The method of claim 11, comprising: determining the lookup word based on a packet; and processing the packet based on processing information acquired based on a matching content-addressable memory entry of the plurality of content-addressable memory entries identified as matching in the accurate result match vector. ### Claim 13 (depends on 12) The method of claim 12, wherein the matching content-addressable memory entry is the highest-priority entry of the plurality of content-addressable memory entries identified as matching in the accurate result match vector. ### Claim 14 An apparatus, comprising: a plurality of content-addressable memory operation portions that collectively perform a lookup operation on a lookup word in a plurality of content-addressable memory entries, with each of the lookup word and said content-addressable memory entries partitioned into a plurality of corresponding portions; wherein each of the plurality of content-addressable memory operation portions includes a plurality of content-addressable memory entry portions that store source vectors, matching logic to produce a portion match vector identifying the result of matching said source vectors in the plurality of content-addressable memory entry portions to a lookup word portion of the lookup word, error-correction unit to process the portion match vector and an error correction code (ECC) to produce an accurate portion match vector; and a result combination logic that generating an accurate result match vector by combining said accurate portion match vector produced by each of the plurality of content-addressable memory operation portions. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein each of the plurality of content-addressable memory operation portions retrieves the ECC from storage based on the lookup word portion. ### Claim 16 (depends on 14) The apparatus of claim 14, wherein each of the plurality of content-addressable memory entries is a binary content-addressable memory entry. ### Claim 17 (depends on 14) The apparatus of claim 14, wherein each of the plurality of content-addressable memory entries is a ternary content-addressable memory entry. ### Claim 18 An apparatus, comprising: a plurality of content-addressable memory entries that store source vectors; matching logic to produce a match vector including an entry match result for each of the plurality of content-addressable memory entries based on a matching between said stored source vectors and a lookup word; an error-correction unit to process the match vector and a particular error correction code (ECC) to produce an accurate portion match vector. ### Claim 19 (depends on 18) The apparatus of claim 18, comprising memory storing an error correction code (ECC) for each of the possible lookup values; wherein the error-correction unit receives the particular ECC retrieved from said memory based on the lookup word. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein each of the plurality of content-addressable memory entries is a binary content-addressable memory entry.