# US 2019/0317731 A1 · Internally truncated multiplier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0317731 A1 - Document ID: US20190317731A1 - Status: Published application - Kind: A1 - Application number: 16/454,369 - Filed: 2019-06-27 - Published: 2019-10-17 - Earliest claimed: 2016-05-04 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Jawaharlal Tangudu; Suvam Nandi; Pooja Sundar; Jaiganesh Balakrishnan - Web page: https://patentgrep.com/patent/US20190317731A1 ## CPC - G06F 7/523: Multiplying only - G06F 7/50: Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) - H03D 7/161: {all the frequency changers being connected in cascade} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66) ## Abstract A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit. ## Claims ### Claim 1 A circuit comprising: a partial product generator configured to: receive a multiplier and a multiplicand; and generate a set of partial products for the multiplier and the multiplicand; a truncation circuit coupled to the partial product generator and configured to: receive the set of partial products; and remove a set of least significant bits from a subset of the set of partial products to produce a set of truncated partial products; a bias compensation circuit configured to: determine a count of non-zero bits that have been removed from the subset of the set of partial products by the truncation circuit; and determine a bias compensation value that is a function of the count; and an adder coupled to the truncation circuit and the bias compensation circuit and configured to: add the set of truncated partial products and the bias compensation value to produce a product. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the bias compensation value equals the count multiplied by a bias multiplier. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the bias multiplier is equal to ½. ### Claim 4 (depends on 1) The circuit of claim 1 further comprising a digital down converter that includes a mixer that includes the partial product generator, the truncation circuit, the bias compensation circuit, and the adder, wherein the mixer is configured to: receive a radio frequency signal and a down conversion frequency; provide the radio frequency signal and the down conversion frequency to the partial product generator as the multiplicand and the multiplier; and provide the product as an intermediate frequency signal. ### Claim 5 (depends on 1) The circuit of claim 1 further comprising a digital up converter that includes a mixer that includes the partial product generator, the truncation circuit, the bias compensation circuit, and the adder, wherein the mixer is configured to: receive a signal to be transmitted and an oscillator signal; and provide the signal to be transmitted and the oscillator signal to the partial product generator as the multiplicand and the multiplier. ### Claim 6 (depends on 1) The circuit of claim 1 further comprising a partial product pre-computation circuit coupled to the partial product generator and configured to provide the multiplicand to the partial product generator as a set of radix-4 variants of the multiplicand. ### Claim 7 (depends on 6) The circuit of claim 6, wherein the partial product generator is configured to perform a radix-4 Booth technique to generate the set of partial products. ### Claim 8 (depends on 7) The circuit of claim 7, wherein: the partial product generator includes a recoding circuit configured to perform radix-4 recoding of the multiplier; and the bias compensation circuit is coupled to receive an output of the recoding circuit and configured to determine the bias compensation value based on the output of the recoding circuit. ### Claim 9 A circuit device comprising: a partial product generator circuit coupled to receive a multiplicand and a multiplier; a truncation circuit coupled to the partial product generator circuit; a bias compensation circuit coupled to the partial product generator circuit and configured to: determine a count of non-zero bits that have been removed by the truncation circuit; and provide a bias compensation value that is equal to the count multiplied by a bias multiplier; and an adder coupled to the truncation circuit and the bias compensation circuit to receive the bias compensation value and configured to add an output of the truncation circuit and the bias compensation value to produce a product of the multiplicand and the multiplier. ### Claim 10 (depends on 9) The circuit device of claim 9, wherein the bias multiplier is equal to ½. ### Claim 11 (depends on 9) The circuit device of claim 9 further comprising a digital down converter that includes the partial product generator circuit, the truncation circuit, the bias compensation circuit, and the adder, wherein the digital down converter is configured to: receive a radio frequency signal and a down conversion frequency; provide the radio frequency signal and the down conversion frequency to the partial product generator circuit as the multiplicand and the multiplier; and provide the product as an intermediate frequency signal. ### Claim 12 (depends on 9) The circuit device of claim 9 further comprising a digital up converter that includes the partial product generator circuit, the truncation circuit, the bias compensation circuit, and the adder, wherein the digital up converter is configured to: receive a signal to be transmitted and an oscillator signal; and provide the signal to be transmitted and the oscillator signal to the partial product generator circuit as the multiplicand and the multiplier. ### Claim 13 (depends on 9) The circuit device of claim 9 further comprising a partial product pre-computation circuit coupled to the partial product generator circuit and configured to provide the multiplicand to the partial product generator circuit as a set of radix-4 variants of the multiplicand. ### Claim 14 (depends on 9) The circuit device of claim 9, wherein the partial product generator circuit is configured to perform a radix-4 Booth technique to generate a set of partial products. ### Claim 15 (depends on 14) The circuit device of claim 14, wherein: the partial product generator circuit includes a recoding circuit configured to perform radix-4 recoding of the multiplier; and the bias compensation circuit is coupled to receive an output of the recoding circuit and configured to determine the bias compensation value based on the output of the recoding circuit. ### Claim 16 A circuit comprising: a partial product generator configured to: receive a multiplier and a multiplicand; and generate a set of partial products for the multiplier and the multiplicand; a truncation circuit coupled to the partial product generator and configured to: receive the set of partial products; and remove a set of least significant bits from a subset of the set of partial products to produce a set of truncated partial products; an adder coupled to the truncation circuit and configured to: add the set of truncated partial products and a bias compensation value to produce a product, wherein the bias compensation value is a function of a count of the subset of the set of partial products from which the set of least significant bits has been removed. ### Claim 17 (depends on 16) The circuit of claim 16, wherein the bias compensation value equals the count multiplied by a bias multiplier. ### Claim 18 (depends on 17) The circuit of claim 17, wherein the bias multiplier is equal to ¼. ### Claim 19 (depends on 16) The circuit of claim 16 further comprising a digital down converter that includes the partial product generator, the truncation circuit, and the adder, wherein the digital down converter is configured to: receive a radio frequency signal and a down conversion frequency; provide the radio frequency signal and the down conversion frequency to the partial product generator as the multiplicand and the multiplier; and provide the product as an intermediate frequency signal. ### Claim 20 (depends on 16) The circuit of claim 16 further comprising a digital up converter that includes the partial product generator, the truncation circuit, and the adder, wherein the digital up converter is configured to: receive a signal to be transmitted and an oscillator signal; and provide the signal to be transmitted and the oscillator signal to the partial product generator as the multiplicand and the multiplier.