# US 2019/0317690 A1 · Semiconductor device and ufs system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0317690 A1 - Document ID: US20190317690A1 - Status: Published application - Kind: A1 - Application number: 16/368,555 - Filed: 2019-03-28 - Published: 2019-10-17 - Earliest claimed: 2018-04-13 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Daisuke MIZOGUCHI - Web page: https://patentgrep.com/patent/US20190317690A1 ## CPC - G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 13/382: {using universal interface adapter} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract When contents of UFSHCI standard are directly implemented in a UFS host, a problem may occur such that read/write operations of a UFS device stop or contents of data are destroyed. A semiconductor device has a UFS host controller that performs data transfer with a universal flash storage (UFS) device. The semiconductor device includes a Run-Stop register that sets the UFS host controller into a processing possible state, a Door bell register that instructs the UFS host controller to perform transfer, and a ready bit that indicates whether or not the UFS host controller can perform processing of transfer request. When the Run-Stop register is cleared while the data transfer is in process, the UFS host controller prevents a next data transfer from being registered until the data transfer is completed. ## Claims ### Claim 1 A semiconductor device that performs data transfer with a Universal Flash Storage (UFS) device, the semiconductor device comprising: a Central Processing Unit (CPU); a UFS host controller; a memory that stores a transfer request list describing processing of the data transfer; a Run-Stop register that is set a first value indicating the processing is executable or a second value not indicating the processing is executable, and a Door bell register that is set a third value instructing the UFS host controller to perform the data transfer according to the transfer request list or a fourth value not instructing the UFS host controller to perform the data transfer according to the transfer request list, the fourth value being set in the Door bell register when the second value is set in the Run-stop register, wherein, when the data transfer is performed, the CPU sets the first value in the Run-stop register and sets the third value in the Door bell register, and wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the UFS host controller prevents the Run-stop register to be set the first value or the Door bell register to be set the third value instructing to perform a next data transfer until the data transfer is completed. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising a ready bit that is set a fifth value indicating the Run-stop register can be set to the first value or a sixth value not indicating the Run-stop register can be set to the first value, wherein, when the data transfer is performed, the UFS host controller sets the fifth value in the ready bit, and wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the UFS host controller prevents the next data transfer by setting the sixth value in the ready bit. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein, when the Run-Stop register is set the second value while the data transfer is in process, the UFS host controller does not set the fifth value to the ready bit until the data transfer is completed. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, further comprising an internal Door bell register that is set a seventh value to hold the transfer state when the Door bell register is set the third value, or an eighth value to hold the transfer state when the Door bell register is set the fourth value, and even when the Run-Stop register is set the second value while the data transfer is in process, the seventh value of the internal Door bell register is held, wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the UFS host controller writes back a value of the internal Door bell register to the Door bell register. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the UFS host controller writes back the seventh value of the internal Door bell register to the Door bell register. ### Claim 6 A semiconductor device that performs data transfer with a universal flash storage (UFS) device, the semiconductor device comprising: a Central Processing Unit (CPU); a transfer control unit; a memory that stores a transfer request list describing processing of the data transfer; a Run-Stop register that is set a first value indicating the processing is executable or a second value not indicating the processing is executable, and a Door bell register that is set a third value instructing the transfer control unit to perform the data transfer according to the transfer request list or a fourth value not instructing the transfer control unit to perform the data transfer according to the transfer request list, the fourth value being set in the Door bell register when the second value is set in the Run-stop register, wherein, when the data transfer is performed, the CPU sets the first value in the Run-stop register and sets the third value in the Door bell register, and wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the transfer control unit prevents the Run-stop register to be set the first value or the Door bell register to be set the third value instructing to perform a next data transfer until the data transfer is completed. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, further comprising a ready bit that is set a fifth value indicating the Run-stop register can be set to the first value or a sixth value not indicating the Run-stop register can be set to the first value, wherein, when the data transfer is performed, the UFS host controller sets the fifth value in the ready bit, and wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the transfer control unit prevents the next data transfer by setting the sixth value in the ready bit. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein, when the Run-Stop register is set the second value while the data transfer is in process, the transfer control unit does not set the fifth value to the ready bit until the data transfer is completed. ### Claim 9 (depends on 6) The semiconductor device according to claim 6, further comprising an internal Door bell register that is set a seventh value to hold the transfer state when the Door bell register is set the third value, or an eighth value to hold the transfer state when the Door bell register is set the fourth value, and even when the Run-Stop register is set the second value while the data transfer is in process, the seventh value of the internal Door bell register is held, wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the transfer control unit writes back a value of the internal Door bell register to the Door bell register. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the transfer control unit writes back the seventh value of the internal Door bell register to the Door bell register. ### Claim 11 A UFS system comprising: a universal flash storage (UFS) device, and a UFS host that controls data transfer with the UFS device, wherein the UFS host includes a Central Processing Unit (CPU), a UFS host controller, a Run-Stop register that sets the UFS host controller into a processing possible state, and a Door bell register that is set a third value instructing the UFS host controller to perform the data transfer according to the transfer request list or a fourth value not instructing the UFS host controller to perform the data transfer according to the transfer request list, the fourth value being set in the Door bell register when the second value is set in the Run-stop register, and wherein, when the data transfer is performed, the CPU sets the first value in the Run-stop register and sets the third value in the Door bell register, and wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the UFS host controller prevents the Run-stop register to be set the first value or the Door bell register to be set the third value instructing to perform a next data transfer until the data transfer is completed. ### Claim 12 (depends on 11) The UFS system according to claim 11, further comprising a ready bit that is set a fifth value indicating the Run-stop register can be set to the first value or a sixth value not indicating the Run-stop register can be set to the first value, wherein, when the data transfer is performed, the UFS host controller sets the fifth value in the ready bit, and wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the UFS host controller prevents the next data transfer by setting the sixth value in the ready bit. ### Claim 13 (depends on 11) The UFS system according to claim 11, further comprising an internal Door bell register that is set a seventh value to hold the transfer state when the Door bell register is set the third value, or an eighth value to hold the transfer state when the Door bell register is set the fourth value, and even when the Run-Stop register is set the second value while the data transfer is in process, the seventh value of the internal Door bell register is held, wherein, when the CPU sets the second value in the Run-stop register while the data transfer is in process, the UFS host controller writes back a value of the internal Door bell register to the Door bell register. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, further comprising a transfer in-process flag (TSF) that is set the ninth value indicating the data transfer from the UFS host controller is in process or the tenth value not indicating the data transfer from the UFS host controller is in process, wherein, when the data transfer is performed, the UFS host controller sets the ninth value in the transfer in-process flag, and wherein, when the CPU sets the second value in the Run-stop register, the UFS host controller prevents the next data transfer based on the transfer in-process flag.