# US 2019/0317587 A1 · Method for performing power management in a memory device, associated memory device and controller thereof, and associated electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0317587 A1 - Document ID: US20190317587A1 - Status: Published application - Kind: A1 - Application number: 16/039,302 - Filed: 2018-07-18 - Published: 2019-10-17 - Earliest claimed: 2018-04-12 - Assignees: Silicon Motion, Inc. - Applicants: Silicon Motion Inc. - Inventors: Tzu-Wei Hsu - Web page: https://patentgrep.com/patent/US20190317587A1 ## CPC - G06F 1/3268: {Power saving in hard disk drive} - G06F 1/32: Means for saving power - G06F 1/3225: of memory devices - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G06F 1/3234: Power saving characterised by the action undertaken - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 2212/1004: Compatibility, e.g. with legacy hardware - G06F 2212/1028: Power efficiency - G06F 2212/7206: Reconfiguration of flash memory system - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A method for performing power management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The memory device includes a non-volatile (NV) memory including at least one NV memory element. The method may include: during an initialization phase of the memory device, detecting whether a host device supports communications corresponding to a first communications protocol; and before detecting that the host device supports communications corresponding to the first communications protocol, controlling a physical layer (PHY) circuit within the memory device to keep staying at a power off state to save power, wherein the PHY circuit supports communications corresponding to the first communications protocol. ## Claims ### Claim 1 A method for performing power management in a memory device, the memory device comprising a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the method comprising: during an initialization phase of the memory device, detecting whether a host device supports communications corresponding to a first communications protocol; and before detecting that the host device supports communications corresponding to the first communications protocol, controlling a physical layer (PHY) circuit within the memory device to keep staying at a power off state to save power, wherein the PHY circuit supports communications corresponding to the first communications protocol. ### Claim 2 (depends on 1) The method of claim 1, wherein the host device outputs a set of driving voltages to the memory device; a power switch circuit within the memory device is coupled between at least one driving voltage of the set of driving voltages and the PHY circuit; and controlling the PHY circuit to keep staying at the power off state is performed through the power switch circuit. ### Claim 3 (depends on 2) The method of claim 2, wherein the at least one driving voltage comprises one or more driving voltages; and the power switch circuit comprises multiple power switches coupled to the one or more driving voltages and arranged to control digital and analog power domains of the PHY circuit, respectively. ### Claim 4 (depends on 1) The method of claim 1, wherein the host device outputs a set of driving voltages to the memory device; in the initialization phase, a first driving voltage of the set of driving voltages is pulled from a ground voltage level to a first voltage level before a specific driving voltage of the set of driving voltages is pulled from the ground voltage level to a second voltage level; and detecting whether the host device supports communications corresponding to the first communications protocol is performed according to the specific driving voltage. ### Claim 5 (depends on 4) The method of claim 4, wherein detecting whether the host device supports communications corresponding to the first communications protocol comprises: performing voltage detection on the specific driving voltage to generate a detection signal; and monitoring a logical state of a specific signal from the host device according to the detection signal to generate a power control signal corresponding to the logical state, for controlling power of the PHY circuit, wherein the specific signal is received by the memory device through a corresponding communications terminal of the memory device, and the power control signal indicates whether the host device supports communications corresponding to the first communications protocol. ### Claim 6 (depends on 5) The method of claim 5, wherein monitoring the logical state of the specific signal from the host device according to the detection signal to generate the output signal corresponding to the logical state comprises: storing one-bit information corresponding to the logical state into a one-bit storage circuit according to the detection signal to generate the power control signal, wherein the detection signal is input into a clock terminal of the one-bit storage circuit, and the power control signal is an output signal of the one-bit storage circuit. ### Claim 7 (depends on 6) The method of claim 6, wherein the one-bit storage circuit is a register or a flip-flop. ### Claim 8 (depends on 6) The method of claim 6, wherein monitoring the logical state of the specific signal from the host device according to the detection signal to generate the output signal corresponding to the logical state comprises: inverting the specific signal to generate an inverted signal of the specific signal; and monitoring the logical state of the specific signal through monitoring a corresponding logical state of the inverted signal, wherein the corresponding logical state is stored as the one-bit information. ### Claim 9 (depends on 6) The method of claim 6, wherein the detection signal is utilized as a clock signal of the one-bit storage circuit. ### Claim 10 (depends on 6) The method of claim 6, wherein an edge of the detection signal indicates a transition of the specific driving voltage. ### Claim 11 (depends on 10) The method of claim 10, wherein there is no subsequent edge of the detection signal during a normal operation phase of the memory device. ### Claim 12 (depends on 1) The method of claim 1, further comprising: when detecting that the host device does not support communications corresponding to the first communications protocol, performing communications corresponding to another communications protocol without using the PHY circuit, to allow the host device to access the memory device. ### Claim 13 (depends on 1) The method of claim 1, further comprising: when detecting that the host device supports communications corresponding to the first communications protocol, controlling the PHY circuit to enter a power on state, for performing communications corresponding to the first communications protocol through the PHY circuit, to allow the host device to access the memory device. ### Claim 14 A memory device, comprising: a non-volatile (NV) memory, arranged to store information, wherein the NV memory comprises at least one NV memory element; and a controller, coupled to the NV memory, arranged to control operations of the memory device, wherein the controller comprises: a processing circuit, arranged to control the controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the controller; and a transmission interface circuit, coupled to the processing circuit, arranged to perform communications with the host device for the memory device; wherein: during an initialization phase of the memory device, the controller detects whether the host device supports communications corresponding to a first communications protocol; and before detecting that the host device supports communications corresponding to the first communications protocol, the controller controls a physical layer (PHY) circuit within the transmission interface circuit to keep staying at a power off state to save power, wherein the PHY circuit supports communications corresponding to the first communications protocol. ### Claim 15 (depends on 14) The memory device of claim 14, wherein the host device outputs a set of driving voltages to the memory device; and the transmission interface circuit comprises: a power switch circuit, coupled between at least one driving voltage of the set of driving voltages and the PHY circuit, wherein through the power switch circuit, the controller controls the PHY circuit to keep staying at the power off state. ### Claim 16 (depends on 14) The memory device of claim 14, wherein the host device outputs a set of driving voltages to the memory device; in the initialization phase, a first driving voltage of the set of driving voltages is pulled from a ground voltage level to a first voltage level before a specific driving voltage of the set of driving voltages is pulled from the ground voltage level to a second voltage level; and according to the specific driving voltage, the controller detects whether the host device supports communications corresponding to the first communications protocol. ### Claim 17 (depends on 16) The memory device of claim 16, wherein the transmission interface circuit comprises: a voltage detection circuit, arranged to perform voltage detection on the specific driving voltage to generate a detection signal; and a power on control circuit, coupled to the voltage detection circuit, arranged to monitor a logical state of a specific signal from the host device according to the detection signal to generate a power control signal corresponding to the logical state, for controlling power of the PHY circuit, wherein the specific signal is received by the memory device through a corresponding communications terminal of the memory device, and the power control signal indicates whether the host device supports communications corresponding to the first communications protocol. ### Claim 18 (depends on 17) The memory device of claim 17, wherein the power on control circuit comprises: a one-bit storage circuit, arranged to store one-bit information corresponding to the logical state, wherein the power on control circuit stores the one-bit information corresponding to the logical state into the one-bit storage circuit according to the detection signal to generate the power control signal, the detection signal is input into a clock terminal of the one-bit storage circuit, and the power control signal is an output signal of the one-bit storage circuit. ### Claim 19 (depends on 14) An electronic device comprising the memory device of claim 14, and further comprising: the host device, coupled to the memory device, wherein the host device comprises: at least one processor, arranged for controlling operations of the host device; and a power supply circuit, coupled to the at least one processor, arranged for providing power to the at least one processor and the memory device; wherein the memory device provides the host device with storage space. ### Claim 20 A controller of a memory device, the memory device comprising the controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the controller comprising: a processing circuit, arranged to control the controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the controller; and a transmission interface circuit, coupled to the processing circuit, arranged to perform communications with the host device for the memory device; wherein: during an initialization phase of the memory device, the controller detects whether the host device supports communications corresponding to a first communications protocol; and before detecting that the host device supports communications corresponding to the first communications protocol, the controller controls a physical layer (PHY) circuit within the transmission interface circuit to keep staying at a power off state to save power, wherein the PHY circuit supports communications corresponding to the first communications protocol.