# US 2019/0317546 A1 · Level-based droop detection

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- Number: US 2019/0317546 A1
- Document ID: US20190317546A1
- Status: Published application
- Kind: A1
- Application number: 15/954,051
- Filed: 2018-04-16
- Published: 2019-10-17
- Earliest claimed: 2018-04-16
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Richard Martin BORN; Stephen Victor KOSONOCKY; Miguel RODRIGUEZ
- Web page: https://patentgrep.com/patent/US20190317546A1

## CPC

- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
- G06F 1/305: {in the event of power-supply fluctuations}
- G06F 1/324: by lowering clock frequency
- H03K 5/00006: {Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.

## Claims

### Claim 1

A method comprising:
providing a clock signal from a clock distribution network to a processing unit;
monitoring a voltage provided to the processing unit;
providing a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage; and
decreasing a frequency of the clock signal by the clock distribution network in response to receiving the droop detection signal.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
interrupting the droop detection signal provided to the clock distribution network in response to the voltage rising above a second threshold voltage; and
increasing the frequency of the clock signal provided to the processing unit by the clock distribution network in response to interruption of the droop detection signal.

### Claim 3 (depends on 2)

The method of claim 2, wherein providing the droop detection signal and interrupting the droop detection signal comprises:
providing and interrupting the droop detection signal a plurality of times in response to a plurality of droops in the voltage that occurred during different time intervals.

### Claim 4 (depends on 3)

The method of claim 3, wherein durations of the different time intervals range from nanoseconds to milliseconds.

### Claim 5 (depends on 2)

The method of claim 2, further comprising:
providing the clock signal at a first frequency prior to the clock distribution network receiving the droop detection signal; and
providing the clock signal at a second frequency in response to the clock distribution network receiving the droop detection signal, wherein the second frequency is lower than the first frequency.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
providing the clock signal at the first frequency in response to interruption of the droop detection signal.

### Claim 7 (depends on 6)

The method of claim 6, wherein:
providing the clock signal at the second frequency comprises increasing a number of oscillations between high and low phases of a phase locked loop that generates the clock signal in response to the clock distribution network receiving the droop detection signal; and
providing the clock signal at the first frequency in response to interruption of the droop detection signal comprises decreasing the number of oscillations between the high and low phases of the phase locked loop in response to interruption of the droop detection signal.

### Claim 8

An apparatus comprising:
a power regulator configured to provide current to a processing unit;
a clock distribution network configured to provide a clock signal to the processing unit;
a level-based droop detector configured to monitor a voltage of the current provided to the processing unit and provide a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage; and
wherein the clock distribution network is configured to decrease a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein:
the level-based droop detector is configured to interrupt the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage; and
the clock distribution network is configured to increase the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the level-based droop detector comprises:
a voltage source configured to generate the threshold voltage; and
a comparator configured to compare the threshold voltage generated by the voltage source to the voltage provided to the processing unit, wherein the comparator is configured to generate the droop detection signal based on the comparison.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the level-based droop detector is configured to provide an interrupt in the droop detection signal a plurality of times in response to a plurality of droops in the voltage that occurred during different time intervals.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the durations of the different time intervals range from nanoseconds to milliseconds.

### Claim 13 (depends on 9)

The apparatus of claim 9, wherein the clock distribution network is configured to:
provide the clock signal at a first frequency prior to the clock distribution network receiving the droop detection signal; and
provide the clock signal at a second frequency in response to receiving the droop detection signal, wherein the second frequency is lower than the first frequency.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the clock distribution network is configured to provide the clock signal at the first frequency in response to interruption of the droop detection signal.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the clock distribution network comprises:
a phase locked loop to provide a fixed rate clock signal; and
a digital frequency synthesizer to provide a variable rate clock signal by modifying the fixed rate clock signal.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the digital frequency synthesizer is configured to provide the clock signal at the second frequency by increasing a number of oscillations between high and low phases of the phase locked loop in response to the clock distribution network receiving the droop detection signal.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the digital frequency synthesizer is configured to provide the clock signal at the first frequency in response to interruption of the droop detection signal by decreasing the number of oscillations between the high and low phases of the phase locked loop in response to interruption of the droop detection signal.

### Claim 18

An apparatus comprising:
a power regulator configured to provide current at a voltage;
at least one clock distribution network configured to provide a first clock signal to a first clock domain and a second clock signal to a second clock domain;
a first level-based droop detector configured to monitor the voltage and provide a first droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage;
a second level-based droop detector configured to monitor the voltage and provide a second droop detection signal to the clock distribution network in response to the voltage falling below a second threshold voltage;
wherein the at least one clock distribution network is configured to decrease a first frequency of the first clock signal provided to the first clock domain in response to receiving the first droop detection signal; and
wherein the at least one clock distribution network is configured to decrease a second frequency of the second clock signal provided to the second clock domain in response to receiving the second droop detection signal.

### Claim 19 (depends on 18)

The apparatus of claim 18, further comprising:
a synchronization network configured to synchronize the first and second clock signals subject to a constraint.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the synchronization network is configured to synchronize the first and second clock signal such that the first frequency is less than or equal to the second frequency.