# US 2019/0317541 A1 · Low power half-vdd generation circuit with high driving capability

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- Number: US 2019/0317541 A1
- Document ID: US20190317541A1
- Status: Published application
- Kind: A1
- Application number: 15/951,894
- Filed: 2018-04-12
- Published: 2019-10-17
- Earliest claimed: 2018-04-12
- Assignees: Analog Devices Global Unlimited Company
- Applicants: Analog Devices Global Unlimited Company
- Inventors: Hanqing Wang; Gerard Mora-Puchalt
- Web page: https://patentgrep.com/patent/US20190317541A1

## CPC

- G05F 3/16: being semiconductor devices
- H03F 3/005: {using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers (H03F3/45 takes precedence)}
- H03F 3/45273: {Mirror types}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03K 17/687: the devices being field-effect transistors
- H03F 2200/129: there being a feedback over the complete amplifier
- H03F 2203/45512: the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC
- H03F 2203/45551: the IC comprising one or more switched capacitors
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- H03F: AMPLIFIERS
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A common mode reference circuit comprises a divider stage and an output stage. The divider stage includes a first n-channel field effect transistor and p-channel filed effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node. The output stage includes a first FET connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and a common mode reference output at a series connection from the first FET to the second FET.

## Claims

### Claim 1

A common mode reference circuit comprising:
a divider stage including:
a first n-channel field effect transistor and p-channel field effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node;
a second NFET/PFET pair connected in series to the first NFET/PFET pair and a low supply voltage circuit node;
a third NFET/PFET pair connected in series to the high supply voltage circuit node; and
a fourth NFET/PFET pair connected in series to the low supply voltage circuit node; and
an output stage including:
a first field effect transistor (FET) connected as a current mirror to a transistor of the first NFET/PFET pair;
a second FET connected as a current mirror to a transistor of the second NFET/PFET pair;
a third FET connected as a current mirror to a transistor of the third NFET/PFET pair; and
a fourth FET connected as a current mirror to a transistor of the fourth NFET/PFET pair; and
a common mode reference output connected to a series connection from the first FET to the second FET of the output stage and to a series connection from the third FET to the fourth FET of the output stage.

### Claim 2 (depends on 1)

The common mode reference circuit of claim 1,
wherein the first and second FETs of the output stage are both PFETs;
wherein a gate region of the NFET of the first NFET/PFET pair is connected to a source region of the PFET of the first NFET/PFET pair, and the first FET of the output stage is connected as a current mirror to the PFET of the first NFET/PFET pair; and
wherein a gate region of the NFET of the second NFET/PFET pair is connected to a source region of the PFET of the second NFET/PFET pair, and the second FET of the output stage is connected as a current mirror to the PFET of the second NFET/PFET transistor pair.

### Claim 3 (depends on 1)

The common mode reference circuit of claim 1, including a resistive circuit element coupled between a drain region of the PFET of the first NFET/PFET pair and a gate region of the first YET of the output stage; and a capacitor coupled to the resistive circuit element and coupled between the gate region of the first FET of the output stage and the series connection from the first FET to the second FET.

### Claim 4 (depends on 1)

The common mode reference circuit of claim 1,
wherein the first and second FETs of the output stage are both NFETs;
wherein a gate region of the PFET of the first NFET/PFET pair is connected to a source region of the NFET of the first NFET/PFET pair, and the first FET of the output stage is connected as a current mirror to the NFET of the first NFET/PFET pair; and
wherein a gate region of the PFET of the second NFET/PFET pair is connected to a source region of the NFET of the second NFET/PFET pair, and the second FET of the output stage is connected as a current mirror to the NFET of the second NFET/PFET pair.

### Claim 5 (depends on 1)

The common mode reference circuit of claim 1, including a resistive circuit element coupled between a drain region of the PFET of the second NFET/PFET pair and a gate region of the second FET of the output stage; and a capacitor coupled to the resistive circuit element and coupled between the gate region of the second FET of the output stage and the series connection from the first FET to the second FET.

### Claim 6 (depends on 1)

The common mode reference circuit of claim 1,
wherein the first and second FETs of the output stage are an NFET and a PFET, respectively;
wherein a gate region of the NFET of the first NFET/PFET pair is connected to a source region of the PFET of the first NFET/PFET pair, and the first of the output stage is connected as current mirror to the NFET of the first NFET/PFET pair; and
wherein a gate region of the NFET of the second NFET/PFET pair is connected to a source region of the PFET of the second NFET/PFET pair, and the second YET of the output stage is connected as a current mirror to the PFET of the second NFET/PFET pair.

### Claim 7 (depends on 1)

The common mode reference circuit of claim 1,
wherein the first and second FETs of the output stage are an NFET and a PFET, respectively;
wherein a gate region of the PFET of the first NFET/PFET pair is connected to a source region of the NFET of the first NFET/PFET pair, and the first FET of the output stage is connected as a current mirror to the NFET of the first NFET/PFET pair;
wherein a gate region of the PFET of the second NFET/PFET pair is connected to a source region of the NFET of the second NFET/PFET pair, and the second FET of the output stage is connected as a current mirror to the PFET of the second. NFET/PFET pair.

### Claim 8

(canceled)

### Claim 9 (depends on 1)

The common mode reference circuit of claim 1,
wherein the first and second FETs of the output stage are both PFETs, and the third and fourth FETs of the output stage are both NFETs;
wherein a gate region of the NFET of the first NFET/PFET pair is connected to a source region of the PFET of the first NFET/PFET pair, and the first FET of the output stage is connected as a current mirror to the PFET of the first NFET/PFET pair;
wherein a gate region of the NFET of the second NFET/PFET pair is connected to a source region of the PFET of the second NFET/PFET pair, and the second FET of the output stage is connected as a current mirror to the PFET of the second NFET/PFET pair;
wherein a gate region of the PFET of the third NFET/PFET pair is connected to a source region of the NFET of the third NFET/PFET pair, and the third FET of the output stage is connected as a current mirror to the NFET of the third NFET/PFET pair; and
wherein a gate region of the PFET of the fourth NFET/PFET pair is connected to a source region of the NFET of the fourth NFET/PFET pair, and the fourth FET is connected as a current mirror to the NFET of the fourth NFET/PFET pair.

### Claim 10 (depends on 1)

The common mode reference circuit of claim 1, including:
a first resistive circuit element arranged between the PFET of the first NFET/PFET pair and the high supply voltage circuit node; and
a second resistive circuit element coupled between the NFET of the fourth NFET/PFET pair and the low supply voltage circuit node.

### Claim 11 (depends on 1)

The common mode reference circuit of claim 1,
wherein the first and third FETs of the output stage are both NFETs, and the second and fourth FETs of the output stage are both PFETs;
wherein a gate region of the NFET of the first NFET/PFET pair is connected to a source region of the PFET of the first NFET/PFET pair, and the first FET of the output stage is connected as current mirror to the NFET of the first NFET/PFET pair; and
wherein a gate region of the NFET of the second NFET/PFET pair is connected to a source region of the PFET of the second NFET/PFET pair, and the second FET of the output stage is connected as a current mirror to the PFET of the second NFET/PFET pair;
wherein a gate region of the PFET of the third NFET/PFET pair is connected to a source region of the NFET of the third NFET/PFET pair, and the third FET of the output stage is connected as a current mirror to the NFET of the third NFET/PFET pair;
wherein a gate region of the PFET of the fourth NFET/PFET pair is connected to a source region of the NFET of the fourth NFET/PFET pair, and the fourth FET of the output stage is connected as a current mirror to the PFET of the fourth NFET/PFET pair.

### Claim 12

An electronic circuit comprising:
a common mode reference circuit including:
a divider stage including:
a first transistor pair connected in series to a high supply voltage rail;
a second transistor pair connected in series to the first transistor pair and a low supply voltage rail;
a third transistor pair connected in series to the high supply voltage rail; and
a fourth transistor pair connected in series to the third transistor pair and the low supply voltage rail; and
a push-pull output stage connected to the divider stage and including:
a first output stage leg coupled to the high supply voltage rail and the low supply voltage rail, the first output stage leg including a first field effect transistor (FET) and a second FET;
a second output stage leg coupled to the high supply voltage rail and the low supply voltage rail, the second output stage leg including a third FET connected as a current mirror to a transistor of the third transistor pair, and a fourth FET connected as a current mirror to a transistor of the fourth transistor pair and connected in series with the third FET; and
a common mode reference output connected to a source region or drain region of each of the first, second, third, and fourth FETs.

### Claim 13 (depends on 12)

The electronic circuit of claim 12,
wherein
the first FET is connected as a current mirror transistor of the first transistor pair; and
the second FET connected as a current mirror to a transistor of the second transistor pair and connected in series with the first FET.

### Claim 14 (depends on 13)

The electronic circuit of claim 13,
wherein each of the first, second, third, and fourth transistor pairs of the divider stage are n-channel field effect transistor and p-channel field effect transistor (NFET/PFET) pairs;
wherein the first FET of the output stage is a HET connected as a current mirror to the PFET of the first transistor pair;
wherein the second FET of the output stage is a PFET connected as a current mirror to the PFET of the second transistor pair;
wherein the third FET of the output stage is an NFET connected as a current mirror to the NFET of the third transistor pair; and
wherein the fourth FET of the output stage is an NFET connected as a current mirror to the NFET of the fourth transistor pair.

### Claim 15 (depends on 14)

The common mode reference circuit of claim 14, including:
a first resistive circuit element arranged between the PFET of the first NFET/PFET pair and the high supply voltage circuit node; and
a second resistive circuit element coupled between the NET of the fourth NFET/PFET pair and the low supply voltage circuit node.

### Claim 16 (depends on 13)

The electronic circuit of claim 13,
wherein each of the first, second, third, and fourth transistor pairs of the divider stage are n-channel field effect transistor and p-channel field effect transistor (NFET/PFET) pairs;
wherein the first FET of the output stage is an PFET connected as a current mirror to the NFET of the first transistor pair;
wherein the second FET of the output stage is a PFET connected as a current mirror to the PFET of the second transistor pair;
wherein the third FET of the output stage is an NFET connected as a current mirror to the NFET of the third transistor pair; and
wherein the fourth FET of the output stage is a PFET connected as a current mirror to a PFET of the fourth transistor pair.

### Claim 17 (depends on 12)

The electronic circuit of claim 12, including an electronic sensor and sensor interface circuit, wherein the sensor interface circuit includes a common mode circuit node and the common mode reference output is coupled to the common mode circuit node of the sensor interface circuit.

### Claim 18 (depends on 12)

The electronic circuit of claim 12,
wherein the first transistor pair of the divider stage includes a first n-channel field effect transistor and p-channel field effect transistor (NFET/PFET) pair; and the second transistor pair of the divider stage includes a second NFET/PFET pair; and
wherein the electronic circuit further includes:
an amplifier circuit; and
a switched capacitor circuit coupled to the common mode reference circuit and the amplifier circuit, wherein the output of the common mode reference circuit is a virtual ground for the switched capacitor circuit.

### Claim 19 (depends on 18)

The electronic circuit of claim 18,
wherein the first and second FETs of the output stage are both PFETs;
wherein a gate region of the NFET of the first NFET/PFET pair is connected to a source region of the PFET of the first NFET/PFET pair, and the first FET of the output stage is connected as a current mirror to the PFET of the first NFET/PFET pair; and
wherein a gate region of the NFET of the second NFET/PFET pair is connected to a source region of the PFET of the second NFET/PFET pair, and the second FET of the output stage is connected as a current mirror to the PFET of the second NFET/PFET pair.

### Claim 20

An electronic circuit comprising:
a common mode reference circuit including:
a divider stage including:
a first n-channel field effect transistor and p-channel field effect transistor (NFET/PFET) pair connected in series to a high supply voltage rail; and
a second NFET/PFET pair connected in series to the first NFET/PFET pair and a low supply voltage rail; and
an output stage including:
a first FET connected as a current mirror to a transistor of the first NFET/PFET pair;
a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and
a common mode reference output at a series connection from the first FET to the second FET; and
a resistive circuit element coupled between a drain region of the PFET of one of the first or second NFET/PFET pair and a gate region of one of the first or second FET of the output stage; and
a capacitor coupled to the resistive circuit element and coupled between the gate region of the first or second FET of the output stage and the series connection from the first FET to the second FET.

### Claim 21 (depends on 18)

The electronic circuit of claim 18,
wherein first and second FETs of the output stage are both NFETs;
wherein a gate region of the PFET of the first NFET/PFET pair is connected to a source region of the NFET of the first NFET/PFET pair, and the first FET of the output stage is connected as a current mirror to the NFET of the first NFET/PFET pair; and
wherein a gate region of the PFET of the second NFET/PFET pair is connected to a source region of the NFET of the second NFET/PFET pair, and the second FET of the output stage is connected as a current mirror to the NFET of the second NFET/PFET pair.

### Claim 22 (depends on 20)

The electronic circuit of claim 20, wherein the resistive circuit element is coupled between the drain region of the PFET of the second NFET/PFET pair and the gate region of the second BET of the output stage; and the capacitor is coupled to the resistive circuit element and coupled between the gate region of the second BET of the output stage and the series connection from the first BET to the second FET.

### Claim 23 (depends on 18)

The electronic circuit of claim 18,
wherein the third transistor pair of the divider stage includes a third NFET/PFET pair connected in series to the high supply voltage circuit node; and the fourth transistor pair of the divider stage includes a fourth NFET/PFET pair connected in series to the low supply voltage circuit node.