# US 2019/0317536 A1 · Techniques in hybrid regulators of high power supply rejection ratio and conversion efficiency > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0317536 A1 - Document ID: US20190317536A1 - Status: Published application - Kind: A1 - Application number: 16/450,873 - Filed: 2019-06-24 - Published: 2019-10-17 - Earliest claimed: 2019-06-24 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Xiaosen Liu; Harish Krishnamurthy; Krishnan Ravichandran; Vivek De; Scott Chiu; Claudia Patricia Barrera Gonzalez; Jing Han; Rajasekhara Madhusudan Narayana Bhatla - Web page: https://patentgrep.com/patent/US20190317536A1 ## CPC - G05F 1/56: using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) - G05F 1/462: {as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic} - G05F 1/467: {Sources with noise compensation} - G05F 1/563: including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation - G05F 1/59: including plural semiconductor devices as final control devices for a single load - G05F 1/595: semiconductor devices connected in series - G05F 1/67: to the maximum power available from a generator, e.g. from solar cell - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed. ## Claims ### Claim 1 An apparatus of a hybrid linear dropout regulator (LDO) comprising: a digital LDO that is coupled to a load of an integrated circuit (IC) at an output node, the digital LDO to provide an output voltage at the output node to supply power to the load; and an analog LDO that is coupled to the output node in parallel with the digital LDO, the analog LDO to provide a complementary voltage to the output node based on a noise in the output voltage; and wherein the digital LDO is coupled to a first rail to receive a first voltage and the analog LDO is coupled to a second rail to receive a second voltage, and wherein the first rail is different from the second rail. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising a digital regulator that is coupled to the analog LDO and the digital LDO to: receive a gate voltage of the analog LDO; and generate a control signal to control the digital LDO, based on the gate voltage of the analog LDO. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the digital regulator is further to determine a value of the control signal based on respective comparisons of the gate voltage to a low reference and a high reference, wherein the low reference is smaller than the high reference. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the value of the control signal is a value of a sequence of bits based on which the digital LDO is operable to switch on at least one power transistor of an array of power transistors of the digital LDO, and the array of power transistors is arranged to provide a current supply to the load. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the low reference is a voltage reference VL, the VL is determined based at least in part on an input voltage of the analog LDO and a maximum value of a target power supply rejection ration (PSRR) of the output voltage. ### Claim 6 (depends on 3) The apparatus of claim 3, wherein the low reference is a voltage reference VL, the VL is determined based on a first equation of V L = V mid - V th - β × I out , A 1 PSRR D , max - 1 V DD - V OUT I out - I out , A - 1 R L × A EA , DC wherein VAA is an input voltage of the analog LDO, Vth is a threshold voltage of a power transistor of the analog LDO, β is a resistor feedback factor of the analog LDO, Iout,A is an output current provided by the analog LDO to the load, AEA,DC is a voltage gain of an error amplifier regarding a DC component, PSRRD,max is a maximum value of a target power supply rejection ration (PSRR) of the output voltage, VDD is an input voltage of the digital LDO, VOUT is the output voltage, Iout is an output current to provide current to the load, and RL is a resistance of the load. ### Claim 7 (depends on 3) The apparatus of claim 3, wherein the high reference is a voltage reference VH, the VH is determined based at least in part on an input voltage of the analog LDO and a minimum value of a target power supply rejection ration (PSRR) of the output voltage. ### Claim 8 (depends on 3) The apparatus of claim 3, wherein the high reference is a voltage reference VH, the VH is determined based on a second equation of V H = V mid - V th - β × I out , A 1 PSRR D , min - 1 V DD - V OUT I out - I out , A - 1 R L × A EA , DC wherein VAA is an input voltage of the analog LDO, Vth is a threshold voltage of a power transistor of the analog LDO, β is a resistor feedback factor of the analog LDO, Iout,A is an output current provided by the analog LDO to the load, AEA,DC is a voltage gain of an error amplifier regarding a DC component, PSRRD,max is a maximum value of a target power supply rejection ration (PSRR) of the output voltage, VDD is an input voltage of the digital LDO, VOUT is the output voltage, Iout is an output current to provide current to the load, and RL is a resistance of the load. ### Claim 9 (depends on 3) The apparatus of claim 3, wherein the digital regulator includes at least two comparators to compare the gate voltage respectively with the high reference and the low reference. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the digital regulator is to determine the value of the control signal to increase a current supply to the load from the digital LDO if the gate voltage is smaller than the low reference. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the digital controller is to determine the value of the control signal to decrease a current supply to the load from the digital LDO if the gate voltage is greater than the high reference. ### Claim 12 (depends on 9) The apparatus of claim 9, wherein the digital controller is to determine the value of the control signal to maintain an existing current supply to the load from the digital LDO if the gate voltage is greater than the low reference and smaller than the high reference. ### Claim 13 (depends on 1) The apparatus of claim 1, further comprising one or more additional analog LDOs coupled in series with the analog LDO and the first rail. ### Claim 14 (depends on 1) The apparatus of claim 1, further comprising at least one analog LDO coupled to the digital LDO in parallel and a third rail of a third voltage. ### Claim 15 (depends on 1) The apparatus of claim 1, wherein the first voltage is different from the second voltage. ### Claim 16 (depends on 1) The apparatus of claim 1, wherein the digital LDO and the analog LDO include p-type devices. ### Claim 17 A circuit, comprising: a first set of digital devices that is to provide a first portion of current to a load, the first set of digital devices are to be controlled by a digital regulator; and a second set of analog devices that is to provide a second portion of current to the load; wherein the second set of analog devices is set to reduce noise in the first portion of current to the load and the system is coupled to the load to provide the first portion of current and second portion of current to the load. ### Claim 18 (depends on 17) The system of claim 17, wherein the first set of digital devices is coupled to a first rail to receive a first voltage and the second set of analog devices is coupled to a second rail to receive second voltage that is different from the first voltage. ### Claim 19 (depends on 17) The system of claim 17, wherein the digital regulator is to: receive a gate voltage of the second set of analog devices; compare the gate voltage to a low reference and high reference respectively, the low reference is smaller than the high reference; and generate a control signal to control a shift register of the first set of digital devices, based on the respective comparisons of the gate voltage, wherein the shift register is to control respective power transistors of the first set of digital devices to be on or off. ### Claim 20 (depends on 17) The system of claim 17, wherein the noise includes a ripple fluctuation introduced by a first rail. ### Claim 21 (depends on 20) The system of claim 20, wherein the noise further includes a high-frequency noise introduced by the first set of digital devices. ### Claim 22 An apparatus of a digital regulator, comprising: at least two comparators to compare a gate voltage of an analog LDO to a low reference and a high reference; and a digital controller to generate a control signal to control a shift register of a digital LDO, based on respective comparisons by the at least two comparators; and wherein respective outputs of the at least two comparators are coupled to corresponding inputs of the digital controller to determine a value of the control signal based on the respective comparisons by the at least two comparators. ### Claim 23 (depends on 22) The apparatus of claim 22, wherein the digital LDO is coupled to a load circuitry at an output node, to provide a first portion of a current supply to the load circuitry at the output node; and the analog LDO is coupled to the load circuitry at the output node in parallel with the digital LDO, to detect a ripple fluctuation in the first portion of the current supply and provide a complementary current to the output node that is to be in an opposite phase with the ripple fluctuation; wherein the digital regulator is coupled to the analog LDO to receive the gate voltage and coupled to the digital analog LDO to control an operation of the digital LDO, and the complementary current is a second portion of the current supply. ### Claim 24 (depends on 23) The apparatus of claim 23, wherein respective values of the low reference and high reference correspond to a range of target power supply rejection ration (PSRR) of the current supply.