# US 2019/0317147 A1 · Scheduling Of Scenario Models For Execution Within Different Computer Threads And Scheduling Of Memory Regions For Use With The Scenario Models

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0317147 A1
- Document ID: US20190317147A1
- Status: Published application
- Kind: A1
- Application number: 16/455,642
- Filed: 2019-06-27
- Published: 2019-10-17
- Earliest claimed: 2014-04-18
- Assignees: Breker Verification Systems
- Applicants: Breker Verification Systems
- Inventors: Adnan Hamid; Kairong Qian; Kieu Do; Joerg Grosse
- Web page: https://patentgrep.com/patent/US20190317147A1

## CPC

- G06F 11/3688: {for test execution, e.g. scheduling of test suites}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/31813: {Test pattern generators}
- G06F 3/0484: for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 11/2205: {using arrangements specific to the hardware being tested}
- G06F 11/25: Testing of logic operation, e.g. by logic analysers
- G06F 11/263: Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers}
- G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30)
- G06F 30/331: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
- G06F 30/3323: using formal methods, e.g. equivalence checking or property checking
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06T 11/26: Drawing of charts or graphs
- G06F 2115/02: System on chip [SoC] design
- G06F 2115/08: Intellectual property [IP] blocks or IP cores
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL

## Abstract

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

## Claims

### Claim 1

A method for testing a system-on-a-chip (SoC), comprising:
receiving one or more computer files having a plurality of application scenario models, wherein each of the plurality of application scenario models is associated with a corresponding expected result that is back propagated from an output of the application scenario model via the application scenario model to generate a stimulus at an input of the application scenario model; and
executing a plurality of computer threads to apply the plurality of application scenario models to test a stage of development of the SoC.

### Claim 2 (depends on 1)

The method of claim 1, wherein the one or more computer files are one or more compiled files.

### Claim 3 (depends on 1)

The method of claim 1, wherein the one or more computer files are one or more test files, the method further comprising:
compiling the one or more test files to generate a compiled file; and
providing the compiled file to a test bench program for said executing the plurality of computer threads.

### Claim 4 (depends on 1)

The method of claim 1, wherein the plurality of computer threads include a first computer thread and a second computer thread and the plurality of application scenario models include a first application scenario model and a second application scenario model, wherein the first computer thread is executed to apply a first portion of the first application scenario model and the second computer thread is execute to apply a second portion of the first application scenario model.

### Claim 5 (depends on 4)

The method of claim 4, wherein the second computer thread is executed to apply a first portion of the second application scenario model and the first computer thread is executed to apply a second portion of the second application scenario model.

### Claim 6 (depends on 1)

The method of claim 1, wherein a number of the plurality of computer threads executed to test the stage of development of the SoC is the same as a number of a plurality of computer threads executed within the SoC.

### Claim 7 (depends on 1)

The method of claim 1, wherein the plurality of application scenario models includes a first application scenario model and a second application scenario model, wherein the first application scenario model includes a first plurality of driver scenario models and a direction of execution of the first plurality of driver scenario models, wherein the second application scenario models include a second plurality of driver scenario models and a direction of execution of the second plurality of driver scenario models.

### Claim 8 (depends on 7)

The method of claim 7, wherein said each of the first plurality of driver scenario models is executed to execute a function performed by a component of the SoC.

### Claim 9 (depends on 7)

The method of claim 7, wherein said each of the second plurality of driver scenario models is executed to execute a function performed by a component of the SoC.

### Claim 10 (depends on 1)

The method of claim 1, wherein said each of the plurality of application scenario models is associated with the corresponding expected result when the corresponding expected result is applied to the output of said each of the plurality of application scenario models.

### Claim 11 (depends on 1)

The method of claim 1, wherein the expected result that is back propagated from the output of the application scenario model via the application scenario model to generate the stimulus at the input of the application scenario model when the expected result is applied to a plurality of functions executed by a plurality of driver scenario models of the application scenario model to determine a value at the input of the application scenario model.

### Claim 12 (depends on 11)

The method of claim 11, wherein the plurality of functions include a first function and a second function, wherein the plurality of driver scenario models include a first driver scenario model and a second driver scenario model, wherein the expected result is applied to the first function executed by the first driver scenario model and to the second function executed by the second driver scenario model to determine the value at the input of the application scenario model.

### Claim 13 (depends on 1)

The method of claim 1, wherein the plurality of computer threads include a first computer thread and a second computer thread and the plurality of application scenario models include a first application scenario model and a second application scenario model, wherein said executing the plurality of computer threads to apply the plurality of application scenario models to test the stage of development of the SoC includes:
executing the first computer thread to execute a first portion of the first application scenario model;
executing the second computer thread to execute a second portion of the first application scenario model and a first portion of the second application scenario model, wherein said executing the first computer thread includes executing a second portion of the second application scenario model.

### Claim 14 (depends on 1)

The method of claim 1, wherein the stage of development includes a software stage of development, wherein the software stage of development includes a subsystem stage or a simulation stage.

### Claim 15 (depends on 1)

The method of claim 1, wherein the stage of development includes a hardware stage of development, wherein the hardware stage of development includes an emulation stage, or a prototyping stage, or a post-silicon stage.

### Claim 16

A method for testing a system-on-a-chip (SoC), the method comprising:
receiving a computer file having a plurality of application scenario models, wherein each application scenario model of the plurality of application scenario models has a plurality of driver scenario models, wherein said each application scenario model has a corresponding test input generated based on a corresponding expected output of said each application scenario model, wherein the corresponding expected output is back propagated via the plurality of driver scenario models of said each application scenario model to generate the corresponding test input, wherein the corresponding test input is one of a plurality of test inputs and the corresponding expected output is one of a plurality of expected outputs; and
applying the plurality of test inputs of the plurality of application scenario models to one or more stages of software development of the SoC and one or more stages of hardware development of the SoC for testing the SoC.

### Claim 17 (depends on 16)

The method of claim 16, wherein the computer file is a compiled file that is compiled from one or more test files having the plurality of application scenario models.

### Claim 18 (depends on 16)

The method of claim 16, wherein each of the plurality of driver scenario models is executed to execute a function performed by a component of the SoC.

### Claim 19 (depends on 16)

The method of claim 16, wherein said each application scenario model includes a direction of execution of the plurality of driver scenario models, wherein the direction of execution provides an order in which the plurality of driver scenario models are executed.

### Claim 20 (depends on 19)

The method of claim 19, wherein the order is according to a schedule for executing the plurality of driver scenario models.

### Claim 21 (depends on 16)

The method of claim 16, wherein the plurality of application scenario models include a first application scenario model and a second application scenario model, wherein the plurality of driver scenario models include a first driver scenario model of the first application scenario model, a second driver scenario model of the first application scenario model, a third driver scenario model of the second application scenario model, and a fourth driver scenario model of the second application scenario model, wherein the plurality of expected outputs include a first expected output and a second expected output, wherein the plurality of test inputs include a first test input and a second test input,
wherein the first expected output is back propagated via the first application scenario model to generate the first test input when a function of the second driver scenario model is applied to the first expected output to determine a first intermediate value at an input of the second driver scenario model and a function of the first driver scenario model is applied to the first intermediate value to determine the first test input,
wherein the second expected output is back propagated via the second application scenario model to generate the second test input when a function of the fourth driver scenario model is applied to the second expected output to determine a second intermediate value at an input of the fourth driver scenario model and a function of the third driver scenario model is applied to the second intermediate value to determine the second test input.

### Claim 22 (depends on 21)

The method of claim 21, wherein the second driver scenario model is the same as the fourth driver scenario model.

### Claim 23 (depends on 16)

The method of claim 16, wherein said applying the plurality of test inputs of the plurality of application scenario models to the one or more stages of software development of the SoC and the one or more stages of hardware development of the SoC for testing the SoC includes:
applying the plurality of test inputs during a subsystem software stage of development of the SoC, a simulation stage of development of the SoC, an emulation stage of development of the SoC, a prototyping stage of development of the SoC, and a post-silicon stage of development of the SoC.

### Claim 24 (depends on 16)

The method of claim 16, wherein the plurality of application scenario models include a first application scenario model and a second application scenario model, wherein the plurality of driver scenario models include a first driver scenario model of the first application scenario model, a second driver scenario model of the first application scenario model, a third driver scenario model of the second application scenario model, and a fourth driver scenario model of the second application scenario model, wherein the plurality of expected outputs include a first expected output and a second expected output, wherein the plurality of test inputs include a first test input and a second test input, wherein said applying the plurality of test inputs of the plurality of application scenario models to the one or more stages of software development of the SoC and the one or more stages of hardware development of the SoC for testing the SoC includes:
applying a function of the first driver scenario model of the first application scenario model to the first test input to determine a first intermediate value;
applying a function of the second driver scenario model of the first application scenario model to the first intermediate value to determine a first test output;
applying a function of the third driver scenario model of the second application scenario model to the second test input to determine a second intermediate value;
applying a function of the fourth driver scenario model of the second application scenario model to the second intermediate value to determine a second test output;
comparing the first test output with the first expected output;
comparing the second test output with the second expected output;
determining that the SoC passed the test based on the comparison of the first test output with the first expected output and the comparison of the second test output with the second expected output.

### Claim 25

A system for testing a system-on-a-chip (SoC), comprising:
one or more processors configured to:
receive one or more computer files having a plurality of application scenario models, wherein each of the plurality of application scenario models is associated with a corresponding expected result that is back propagated from an output of the application scenario model via the application scenario model to generate a stimulus at an input of the application scenario model; and
execute a plurality of computer threads to apply the plurality of application scenario models to test a stage of development of the SoC; and
one or more memory devices coupled to the one or more processors, wherein the one or more memory devices are configured to store the corresponding expected result.

### Claim 26 (depends on 25)

The system of claim 25, wherein the plurality of computer threads include a first computer thread and a second computer thread and the plurality of application scenario models include a first application scenario model and a second application scenario model, wherein the first computer thread is executed to apply a first portion of the first application scenario model and the second computer thread is execute to apply a second portion of the first application scenario model.

### Claim 27 (depends on 25)

The system of claim 25, wherein a number of the plurality of threads executed to test the stage of development of the SoC is the same as a number of a plurality of threads executed within the SoC.