Apparatuses and methods for logic/memory devices
AssigneeMicron Technology, Inc.
InventorRichard C. Murphy
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.
Claims20
An apparatus, comprising:
- a plurality of memory components adjacent to and coupled to one another, wherein each of the plurality of memory components comprises a plurality of partitioned banks;
- and
- a logic component comprising a plurality of partitioned logic, each partitioned logic coupled to a subset of the plurality of partitioned banks;
- wherein each of the plurality of partitioned banks comprises:
- an array of memory cells;
- sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component;
- and
- timing circuitry coupled to the array and sensing circuitry, the timing circuitry configured to control timing of operations for the sensing circuitry;
- and
- wherein each of the plurality of partitioned logic comprises control logic coupled to a plurality of timing circuitries of a respective subset, the control logic configured to execute instructions to cause the sensing circuitry to perform the operations.
A method for operating a logic/memory device, comprising:
- responsive to receiving processing in memory (PIM) requests and memory array requests at a logic die of the logic/memory device, routing, by switching circuitry of the logic die, the PIM requests and the memory array requests to perform logical operations and memory operations using sensing circuitry;
- and
- using timing circuitry on the memory die to provide timing for the logical operations on the memory die.
An apparatus, comprising:
- method for operating a memory device:
- a memory die comprising a plurality of first partitioned logics;
- and
- a logic die configured to receive processing in memory (PIM) requests;
- wherein the logic die comprises a second partitioned logic configured to route the received PIM request to a partitioned logic of the plurality of first partitioned logics on which the respective logical operation associated with the PIM requests are to be performed;
- and
- wherein the partitioned logic of the plurality of first partitioned logics is configured to provide timing for the respective logical operations corresponding to the received PIM requests.
Dependencies are inferred from the claim text.