Parallel bit interleaver

A bit interleaver comprising:

• a receiving circuit configured to receive a codeword generated according to a repeat-accumulate quasi-cyclic low-density parity check coding scheme, the codeword including N bit groups each consisting of Q bits;
• a group reordering circuit configured to reorder the N bit groups;
• a bit reordering circuit connected to the group reordering circuit to reorder bits in the codeword;
• a dividing circuit connected to the bit reordering circuit to divide the codeword into constellation words, each of the constellation words being made up of M bits, wherein N is not a multiple of M, X is a remainder of N divided by M, and N′ is equal to N−X, and
• the bit reordering circuit writes bits of N′ bit groups into an M by N matrix row-by-row and the bit reordering circuit reads the written bits of the N′ bit groups from the M by N matrix column-by-column in order to reorder the bits in the codeword.

A reception method comprising:

• receiving a transmission signal through an antenna;
• generating constellation words based on the transmission signal, the constellation words each consisting of M bits;
• generating a codeword by concatenating the constellation words, the codeword including N×Q bits;
• reordering bits in the codeword;
• determining N bit groups of the codeword;
• reordering the N′ bit groups among the N bit groups;
• and
• decoding bits of the codeword according to a low-density parity check coding scheme after the N′ bit groups are reordered, a parity-check matrix of the low-density parity check coding scheme having a quasi-cyclic structure, wherein N is not a multiple of M, X is a remainder of N divided by M, and N′ is equal to N−X, and
• bits of the N′ bit groups are written into an M by N matrix column-by-column and the written bits of the N′ bit groups are read from the M by N matrix row-by-row in order to reorder the bits in the codeword.