Sigma-delta analog-to-digital converter with multiple counters

A sigma-delta analog-to-digital converter (ADC), comprising:

• a first set of switches configured to receive a first voltage signal;
• a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal;
• an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal;
• a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal;
• and
• a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator,
• wherein the processor is configured to increment a first counter value of the first counter based on the second output signal and a second counter value of the second counter based on the second output signal,
• wherein the processor is configured to compute a value based on the first and second counter values;
• wherein the controller unit is configured to change the first output signal based on the second output signal;
• wherein if the second output signal is 1, the controller unit is configured to subtract the first output signal by the second voltage signal, wherein if the second output signal is 0, the controller unit is configured to add the first output signal with first voltage signal.