Apparatuses and methods for detecting a loop count in a delay-locked loop
AssigneeMicron Technology, Inc.
InventorYasuo Satoh
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.
Claims20
An apparatus comprising:
- a delay-locked loop configured to synchronize clock signals internal to a memory with an externally received clock signal;
- a measure controlled delay circuit configured to initialize the delay-locked loop by traversing the delay-locked loop with a reference clock to determine a variable delay amount;
- and
- a loop counter coupled to a divided clock portion of the measure controlled delay circuit, the loop counter having a first section configured to count clock cycles on a first divided clock signal and a second section configured to count clock cycles on a second divided clock signal.
Am apparatus comprising:
- a delay-locked loop configured to synchronize an output clock signal with an input clock signal;
- a first clock divider circuit configured to divide a reference clock signal into multiple portions, the reference clock signal based on the input clock signal;
- a second clock divider circuit configured to divide a feedback signal, wherein the output clock signal is based on the feedback signal;
- a synchronizer circuit configured to provide a measurement pulse signal based on the divided feedback signal and the divided reference clock signal;
- and
- a loop counter circuit configured to start a count based on the divided reference clock signal and stop the count based on the measurement pulse signal, the loop counter circuit comprising an adder configured to sum counts of each portion of the divided reference clock signal.
A method comprising:
- synchronizing clock signals internal to a memory with an externally received clock signal with a delay-locked loop;
- initializing the delay-locked loop with a measure controlled delay circuit by traversing the delay-locked loop with a reference clock to determine the variable delay amount;
- and
- dividing the reference clock into multiple portions;
- and
- counting each of the multiple portions of the reference clock with a different section of a loop counter.
Dependencies are inferred from the claim text.