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US 2019/0296747 A1Published application
Apparatus to improve lock time of a frequency locked loop
AssigneeIntel Corporation
InventorsPraveen Mosalikanti, Qi Wang, Mark L. Neidengard, Vaughn J. Grossnickle, Nasser A. Kurd
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Abstract
An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
Claims20
An apparatus comprising:
- a ring oscillator comprising delay stages including a first delay stage and a second delay stage, wherein the ring oscillator is coupled to a power supply rail;
- and
- a plurality of counters including a first set of counters and a second set of counters, wherein the first set of counters is coupled to the first delay stage, and wherein a second set of counters is coupled to the second delay stage.
An apparatus comprising:
- a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL;
- and
- one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
A system comprising:
- a memory;
- a processor coupled to the memory, wherein the processor includes:
- a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL;
- and
- one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL;
- and
- a wireless interface to allow the processor to communicate with another device.
4 more elements
Dependencies are inferred from the claim text.