Adaptive aging tolerant apparatus

A system-on-chip (SoC) comprising:

• a memory;
• a processor coupled to the memory, wherein the processor comprises:
• a plurality of intellectual property (IP) blocks coupled together in a ring configuration, wherein each IP block comprises:
• a first ring oscillator comprising a non-aging tolerant circuitry;
• and
• a first counter coupled to the first ring oscillator, wherein the first counter is to count a frequency of the first ring oscillator;
• and
• a controller coupled to each of the IP blocks, wherein the controller comprises:
• a second ring oscillator comprising an aging tolerant circuitry;
• a second counter coupled to the second ring oscillator, wherein the second counter is to count a frequency of the second ring oscillator;
• and
• logic to compare the frequencies of the first and second ring oscillators, and to generate one or more controls to mitigate aging of one or more devices;
• and
• a wireless interface to allow the processor to couple to another device.

An apparatus comprising:

• a comparator to compare frequencies of first and second ring oscillators;
• logic coupled to the comparator and to generate one or more controls to mitigate aging of one or more devices, wherein:
• the first ring oscillator comprises at least one aging tolerant circuitry;
• the second ring oscillator comprises a non-aging tolerant circuitry;
• the first ring oscillator is coupled to a first counter, wherein the first counter is to count a frequency of the first ring oscillator, wherein the first counter is coupled to a filter;
• and
• the second ring oscillator is coupled to a second counter, wherein the second counter is to count a frequency of the second ring oscillator.