US 2019/0296744 A1 · COARSE-GRAIN PROGRAMMABLE ROUTING NETWORK FOR LOGIC DEVICES

Abstract

Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.

Claims20

Dependent claims

Circuitry, comprising:

a first die that includes fine-grain routing wires, wherein the fine-grain routing wires have variable routing lengths;
and
a second die that includes a coarse-grain routing network, wherein the coarse-grain routing network includes a plurality of channels forming a deterministic routing path with guaranteed timing closure, and wherein global routing for the first die is performed using the coarse-grain routing network on the second die.

Dependencies are inferred from the claim text.

Coarse-grain programmable routing network for logic devices

Life of this patent

Coarse-grain programmable routing network for logic devices

Life of this patent

Abstract

Claims20