Superconducting magnetic field programmable gate array
AssigneeUniversity of Southern California
InventorsMASSOUD PEDRAM, NAVEEN KATAM, OLEG MUKHANOV
Life of this patent
Estimating the term…
Abstract
A superconducting field programmable gate array (SuperFPGA) apparatus for implementing a superconducting electronic circuit includes a superconducting logic core that includes a plurality of superconducting single flux quantum configurable logic blocks having regular Josephson junctions and inductors that are interconnectible to each other and to input/output terminals of the superconducting electronic circuit. The SuperFPGA apparatus also includes a superconducting routing network, a zero-static-power dissipation biasing network, magnetic Josephson junctions, and a magnetic Josephson junction programming layer.
Claims40
A superconducting field programmable gate array (SuperFPGA) apparatus for implementing a superconducting electronic circuit, comprising:
- a superconducting logic core comprising a plurality of superconducting single flux quantum configurable logic blocks that includes regular Josephson junctions and inductors that are interconnectible to each other and to input/output terminals of the superconducting electronic circuit;
- a superconducting routing network comprising a collection of transmission lines, programmable connection blocks, and programmable switchboxes for realizing connections among the superconducting single flux quantum configurable logic blocks and input/output terminals;
- a zero-static-power dissipation biasing network for supplying desired amounts of biasing currents to the superconducting logic core and superconducting routing network;
- magnetic Josephson junctions used selectively in the zero-static-power dissipation biasing network to enable in-field programmability of the said superconducting logic core and superconducting routing network by changing amounts of locally-provided biasing currents;
- and
- a magnetic Josephson junction programming layer comprising of decoders and superconducting current-carrying lines to enable and effect selective setting of critical current levels of the magnetic Josephson junctions.
The SuperFPGA apparatus claim of 18 wherein a clock-follow-data scheme can be used for reset-pulse distribution in case of operation in an asynchronous wave-pipelined manner.
A method of enabling in-field programmability of a superconducting field programmable logic circuit, comprising:
- receiving programming data describing a desired functionality of the superconducting field programmable logic circuit;
- decoding the programming data to produce a bit stream for programming individual configurable logic blocks and interconnections among configurable logic blocks and primary inputs/outputs of the superconducting field programmable logic circuit;
- and
- processing the bit stream by selectively changing a magnitude of a current flowing in a superconducting line to cause a change in a critical current level of a nearby magnetic Josephson junction, the change causing a corresponding a change in biasing current level supplied to a target superconducting programmable logic or interconnect element.
A feeding clock choking system in a superconducting electronic circuit, comprising
- a plurality of circuit blocks within the superconducting electronic circuit;
- a plurality of magnetic Josephson junction-based switches placed at the start of the feeding Josephson Transmission lines for each of the said plurality of circuit blocks;
- and
- circuitry to program each of the said magnetic Josephson junction-based switches to stop propagation of the feeding clock when there is no circuit activity in a corresponding circuit block.
A method of choking a feeding clock in a superconducting electronic circuit partitioned into a plurality of circuit blocks, comprising
- placing a plurality of magnetic Josephson junction-based switches at the start of the feeding Josephson Transmission lines for each of the said plurality of circuit blocks;
- programming each of the said magnetic Josephson junction-based switches to stop propagation of the feeding clock when there is no circuit activity in a corresponding circuit block.
Dependencies are inferred from the claim text.