Output impedance calibration for signaling

An apparatus, comprising:

• a multi-leg driver that comprises a first partition and a second partition, wherein the first partition is configured to output first data and the second partition is configured to output second data;
• a controller coupled with the multi-leg driver, the controller configured to determine an output impedance of at least one of the first partition or the second partition, wherein the first data output from the first partition comprises multiple bits including a most-significant bit of data, and the second data output from the second partition comprises multiple bits including a least-significant bit of data;
• a first transistor coupled with a first leg group of the first partition, the first transistor configured to adjust an impedance level of at least one leg of the first leg group based at least in part on the controller determining the output impedance of the at least one of the first partition or the second partition;
• a second transistor coupled with at least one leg of a second leg group of the first partition, the second transistor configured to adjust a voltage level of the at least one leg of the second leg group based at least in part on the controller determining the output impedance of the at least one of the first partition or the second partition;
• and
• a second resistive component coupled with the leg group, wherein the second resistive component is configured to adjust an impedance level of the first partition based at least in part on the second transistor adjusting a voltage level of the at least one leg of the second leg group.

An apparatus, comprising:

• a first partition of a driver comprising a first driver configured to output first data, the first driver configured to adjust an impedance level of the first partition from a first impedance level to a second impedance level;
• a second partition of the driver comprising a second driver configured to output second data, the second driver configured to adjust an impedance level of the second partition based at least in part on a resistance level of a resistor coupled with the second partition, wherein an impedance level of the first data output from the first partition is offset from an impedance level of the second data output from the second partition;
• and
• a controller coupled with the driver, the controller configured to determine an output impedance of the first partition, the second partition, or both.

An apparatus, comprising:

• a first partition of a driver comprising a first driver configured to output first data, the first driver configured to adjust an impedance level of the first partition from a first impedance level to a second impedance level;
• a second partition of the driver comprising a second driver configured to output second data, the second driver configured to adjust an impedance level of the second partition based at least in part on a resistance level of a resistor coupled with the second partition, wherein the second partition of the driver further comprises a third driver coupled with the second driver, the third driver configured to adjust the impedance level of the second partition;
• and
• a controller coupled with the driver, the controller configured to determine an output impedance of the first partition, the second partition, or both, and wherein the third driver is configured to adjust the impedance level of the second partition based at least in part on the controller determining the output impedance of the first partition.

A method, comprising:

• receiving first data at a first partition of a memory device, the first partition comprising a first driver;
• adjusting, by the first driver, an impedance level of the first data from a first impedance level to a second impedance level based at least in part on a voltage of the first driver;
• receiving second data at a second partition of the memory device, the second partition comprising a second driver;
• adjusting, by the second driver, an impedance level of the second data from a third impedance level to a fourth impedance level based at least in part on a resistance level of the second driver;
• and
• outputting, from the memory device, the first data having the second impedance level and the second data having the fourth impedance level based at least in part on adjusting the first data and adjusting the second data, wherein the second impedance level of the first data and the fourth impedance level of the second data are different impedance levels.

A method, comprising:

• receiving first data at a first partition of a memory device, the first partition comprising a first driver;
• adjusting, by the first driver, an impedance level of the first data from a first impedance level to a second impedance level based at least in part on a voltage of the first driver;
• receiving second data at a second partition of the memory device, the second partition comprising a second driver;
• adjusting, by the second driver, an impedance level of the second data from a third impedance level to a fourth impedance level based at least in part on a resistance level of the second driver;
• receiving a portion of the second data at a third driver of the second partition of the memory device;
• adjusting, by the third driver, an impedance level of the portion of the second data from the third impedance level to a fifth impedance level;
• outputting, from the third driver, the portion of the second data based at least in part on adjusting the impedance level of the portion of the second data, wherein outputting the second data having the fourth impedance level is based at least in part on outputting the portion of the second data;
• and
• outputting, from the memory device, the first data having the second impedance level and the second data having the fourth impedance level based at least in part on adjusting the first data and adjusting the second data.