Back to results
US 2019/0296734 A1Published application
Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsYoshisato YOKOYAMA, Toshiaki SANO
Life of this patent
Estimating the term…
Abstract
A MOS transistor is allowed to recover from BTI degradation even when an operation mode signal is inactive. A semiconductor device includes a drive circuit coupled to a controlled circuit via a delay element. The drive circuit includes first and second MOS transistors coupled in series to each other. The first MOS transistor is controlled to be in an OFF state when the operation mode signal is active. When the operation mode signal is inactive, the first MOS transistor is controlled to be in the OFF state at least temporarily while the second MOS transistor is controlled to be in the OFF.
Claims18
A semiconductor device, comprising:
- a delay element;
- a drive circuit which is coupled to the delay element, and controls the first circuit;
- and
- a control circuit which controls the drive circuit,
- wherein the drive circuit includes:
- a first MOS transistor coupled between a first power supply node and the delay circuit;
- a second MOS transistor having the first conductivity type which is coupled in series to the first MOS transistor, and coupled between the first power supply node and the delay circuit;
- a third MOS transistor coupled in parallel to the first and second MOS transistors between the first power supply node and the delay circuit;
- and
- a fourth MOS transistor coupled between a second power supply node and the delay circuit,
- wherein, when an operation mode signal is inactive and a clock signal is inactive, the control circuit controls the second MOS transistor into an OFF state and controls the first MOS transistor into the OFF state at least temporarily.
8 more elements
A semiconductor device, comprising:
- a delay element;
- a drive circuit which is coupled to a first circuit via the delay element, and controls the first circuit;
- and
- a control circuit which controls the drive circuit,
- wherein the drive circuit includes:
- an output node coupled to the delay element;
- a first MOS transistor having a first conductivity type and coupled between a first power supply node and the output node;
- and
- a second MOS transistor having the first conductivity type which is coupled in series to the first MOS transistor, and coupled between the first power supply node and the output node,
- wherein, when a first operation mode signal is active, the control circuit controls the first and second MOS transistors into an OFF state,
- wherein, when the first operation mode signal is inactive and a second operation mode signal is active, the control circuit controls the first MOS transistor into the OFF state and controls the second MOS transistor into an ON state or the OFF state depending on whether a clock signal is active or inactive, and
- wherein, when each of the first and second operation mode signals is inactive, the control circuit controls the first MOS transistor into the ON state and controls the second MOS transistor into the ON or OFF state depending on whether the clock signal is active or inactive.
9 more elements
A semiconductor device, comprising:
- a plurality of memory modules,
- wherein each of the memory modules includes:
- a memory cell array;
- a first delay line;
- a second delay line;
- a sense amplifier which starts to operate when a signal at an output terminal of the first delay line is activated;
- a drive circuit having an output node coupled to an input terminal of the first delay line;
- and
- a control circuit which controls the drive circuit,
- wherein the drive circuit includes:
- a first MOS transistor having a first conductivity type, and coupled between a first power supply node and the output node;
- and
- a second MOS transistor having the first conductivity type which is coupled in series to the first MOS transistor, and coupled between the first power supply node and the output node,
- wherein, when a first operation mode signal is active, the control circuit controls the first and second MOS transistors into an OFF state,
- wherein, when the first operation mode signal is inactive and a second operation mode signal is active, the control circuit controls the first MOS transistor into the OFF state and controls the second MOS transistor into an ON state or the OFF state depending on whether a clock signal is active or inactive,
- wherein, when each of the first and second operation mode signals is inactive, the control circuit controls the first MOS transistor into the ON state and controls the second MOS transistor into the ON or OFF state depending on whether the clock signal is active or inactive,
- wherein the memory modules are divided into a plurality of groups,
- wherein the second operation mode signal can be output to another of the memory modules after passing through the second delay line,
- wherein the respective second delay lines of the individual memory modules are coupled together into a chain-like configuration through respective portions of the memory modules, and
- wherein the second operation mode signal is transmitted through the second delay line of each of the memory modules.
17 more elements
Dependencies are inferred from the claim text.