Correction circuit
AssigneeToshiba Memory Corporation
InventorsYasuhiro HIRASHIMA, Masaru KOYANAGI
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Abstract
A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.
Claims20
A correction circuit comprising:
- a first detection unit that is configured to measure a first period of a high level of a first clock;
- a second detection unit that is configured to measure a second period of a high level of a second clock that is complementary to the first clock;
- a delay unit that is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period;
- and
- a waveform shaping unit that is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.
A semiconductor device comprising an input/output circuit that includes a correction circuit configured to correct a duty cycle of a first clock and a functional circuit to which the corrected clock is supplied, wherein the correction circuit includes:
- a first detection unit that is configured to measure a first period of a high level of the first clock;
- a second detection unit that is configured to measure a second period of a high level of a second clock that is complementary to the first clock;
- a delay unit that is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period;
- and
- a waveform shaping unit that is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.
A method of correcting a duty cycle of a first clock, said method comprising:
- measuring a first period of a high level of the first clock;
- measuring a second period of a high level of a second clock that is complementary to the first clock;
- generating a first delay clock and a second delay clock according to a difference between the first period and the second period;
- and
- generating a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.
Dependencies are inferred from the claim text.