Lower power auto-zeroing receiver incorporating ctle, vga, and dfe

An apparatus comprising:

• a first half-cell comprising a first input stage and a first auto-zero stage, wherein said first input stage is configured to present a first input signal to said first auto-zero stage;
• a second half-cell comprising a second input stage and a second auto-zero stage, wherein said second input stage is configured to present a second input signal to said second auto-zero stage;
• and
• a multiplexer configured to (a) receive a first output from said first auto-zero stage, (b) receive a second output from said second auto-zero stage and (c) present one of said first output and said second output, wherein (i) said first half-cell and said second half-cell implement a capacitive coupling, (ii) said capacitive coupling provides a rail-to-rail common-mode input range, (iii) said first half-cell and said second half-cell are configured to prevent a mismatch between data signals and clock signals and (iv) said first half-cell and said second half-cell are each configured to implement a calibration when idle.