Methods of Manufacturing Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
AssigneeSpin Memory, Inc.
InventorSatoru Araki
Life of this patent
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Abstract
A Magnetic Tunnel Junction (MTJ) can include an annular structure and a planar reference magnetic layer disposed about the annular structure. The annular structure can include an annular non-magnetic layer disposed about an annular conductive layer, an annular free magnetic layer disposed about the annular non-magnetic layer, and an annular tunnel insulator disposed about the annular free magnetic layer. The planar reference magnetic layer can be separated from the free magnetic layer by the annular tunnel barrier layer.
Claims23
A method of manufacturing a Magnetic Tunnel Junction (MTJ) comprising;
- forming a first planar non-magnetic insulator layer;
- forming a planar reference magnetic layer on the first planar non-magnetic insulator layer;
- forming a second planar non-magnetic insulator layer on the planar reference magnetic layer;
- forming one or more annular openings through the second planar non-magnetic insulator layer, the planar reference magnetic layer and the first planar non-magnetic insulator layer;
- forming an annular tunnel insulator on the walk of the one or more annular openings;
- forming an annular free magnetic layer on the annular insulator inside the one or more annular openings;
- forming an annular non-magnetic layer on the annular free magnetic layer inside the one or more annular openings;
- and
- forming an annular conductive core inside the annular non-magnetic layer in the one or more annular openings.
A method of manufacturing a memory cell array comprising:
- forming a first planar non-magnetic insulator layer on a plurality of selectors;
- forming a first planar reference magnetic layer on the first planar non-magnetic insulator layer;
- forming a second planar non-magnetic insulator layer on the first planar reference magnetic layer;
- forming a first array of annular openings through the second planar non-magnetic insulator layer, the first planar reference magnetic layer and the first planar non-magnetic insulator layer;
- forming an annular tunnel insulator on the walls of the first array of annular openings;
- forming an annular free magnetic layer on the annular insulator inside the first array of annular openings;
- forming an annular non-magnetic layer on the annular free magnetic layer inside the first array of annular openings;
- and
- forming an annular conductive core inside the annular non-magnetic layer in the first array of annular openings.
The method of manufacturing a memory cell array according to 10, further comprising:
- selectively removing a portion of the fourth planar non-magnetic insulator layer, the second planar reference magnetic layer, the third planar non-magnetic layer and the second planar non-magnetic insulator layer in a periphery region to expose the first and second planar reference magnetic layers;
- forming a first bit line on the portion of the exposed first planar reference magnetic layer and a second bit line on the portion of the exposed second planar reference magnetic layer.
The method of manufacturing a memory cell array according to 11, further comprising:
- forming a first global bit line coupled to the first bit line and one or more additional bit lines in a first row;
- and
- forming a second global bit line coupled to the second bit line and one or more additional bit lines in a second row.
A method of manufacturing a memory cell array comprising:
- forming a first planar non-magnetic insulator layer on a plurality of selectors;
- forming a first planar reference magnetic layer on the first planar non-magnetic insulator layer;
- forming a second planar non-magnetic insulator layer on the first planar reference magnetic layer;
- forming a third planar non-magnetic insulator layer on the second planar non-magnetic insulator layer;
- forming a second planar reference magnetic layer on the third planar non-magnetic insulator layer;
- forming a fourth planar non-magnetic insulator layer on the second planar reference magnetic layer;
- forming an array of annular openings through the fourth planar non-magnetic insulator layer, the second planar reference magnetic layer, the third and second planar non-magnetic insulator layers, the first planar reference magnetic layer and the first planar non-magnetic insulator layer;
- forming an annular tunnel insulator on the walls of the array of annular openings;
- forming an annular free magnetic layer on the annular insulator inside the array of annular openings;
- forming non-magnetic regions in the annular free magnetic layer to separate the annular free magnetic layer into a plurality of portions aligned with the first and second planar reference magnetic layers;
- forming an annular non-magnetic layer on the annular free magnetic layer inside the array of annular openings;
- and
- forming an annular conductive core inside the annular non-magnetic layer in the array of annular openings.
The method of manufacturing a memory cell array according to 16, further comprising:
- selectively removing a portion of the fourth planar non-magnetic insulator layer, the second planar reference magnetic layer, the third planar non-magnetic layer and the second planar non-magnetic insulator layer in, a periphery region to expose the first and second planar reference magnetic layers;
- forming a first bit line on the portion of the exposed first planar reference magnetic layer and a second bit line on the portion of the exposed second planar reference magnetic layer.
The method of manufacturing a memory cell array according to 17, further comprising:
- forming a first global bit line coupled to the first bit line and one or more additional bit lines in a first row;
- and
- forming a second global bit line coupled to the second bit line and one or more additional bit lines in a second row.
The method of manufacturing the memory cell array according to claim 21, wherein the annular tunnel insulator, the annular free magnetic layer and the annular non-magnetic layer are deposited on the sidewalls of the array of annular openings using a directional deposition process.
Dependencies are inferred from the claim text.