Bit Line Structures for Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer

A device comprising:

• a first plurality of annular structures, each annular structure including an annular non-magnetic layer disposed about an annular conductive layer, an annular free magnetic layer disposed about the annular non-magnetic layer, and an annular tunnel insulator disposed about the annular free magnetic layer;
• a first planar reference magnetic layer disposed about the first plurality of annular structures and separated from the free magnetic layers of the first plurality of annular structures by the annular tunnel barrier layers of the first plurality of annular structures;
• first non-magnetic insulator layer disposed about the first plurality of annular structures and on a first side of the first planar reference magnetic layer;
• a second non-magnetic insulator layer disposed about the first plurality of annular structures and on a second side of the first planar reference magnetic layer;
• a second plurality of annular structures axially aligned with respective ones the first plurality of annular structures;
• a second planar reference magnetic layer disposed about the second plurality of annular structures and separated from the free magnetic layer of the second plurality of annular structures by the annular tunnel barrier layers of the second plurality of annular structures;
• a third non-magnetic insulator layer disposed about the second plurality of annular structures and between the second non-magnetic insulator layer and a first side of the second planar reference magnetic layer;
• a fourth non-magnetic insulator layer disposed about the second plurality of annular structures and on a second side of the second planar reference magnetic layer;
• a first bit line coupled to the first planar reference magnetic layer;
• and
• a second bit line coupled to the second planar reference magnetic layer.

A memory device comprising:

• an array of Magnetic Tunnel Junction (MTJ) cells arranged in cell contains and cell rows in a plurality of cell levels, wherein the MTJ cells in corresponding cell column and cell row positions in the plurality of cell levels are coupled together in cell strings, the MTJ cells in each cell string include;
• an annular structure including an annular non-magnetic layer disposed about an annular conductive layer, a plurality of annular free magnetic layers disposed about the annular non-magnetic layer, the annular free magnetic layer separated from each other by corresponding ones of a plurality of non-magnetic separator layers, and an annular tunnel insulator disposed about the annular free magnetic layer;
• a portion of corresponding ones of planar reference magnetic layers disposed about the annular structure and aligned with a corresponding ones of the plurality of portions of the free magnetic layer;
• a portion of one or more planar non-magnetic insulator layers disposed on a first side of each of the plurality of planar reference magnetic layer and about the annular structure;
• a portion of one or more other planar non-magnetic insulator layers disposed on a second side of each of the plurality of planar reference magnetic layer and about the annular structure;
• a plurality of bit lines, wherein respective bit lines are disposed on and electrically coupled to respective planar magnetic layers of respective cell levels;
• and
• a plurality of select elements arranged in, select columns and select rows, wherein respective selector elements are coupled to respective strings of MTJ cells in corresponding cell column and cell row positions.

A device comprising:

• a plurality of annular structures, each annular structure including an annular non-magnetic layer disposed about an annular conductive layer, a first annular free magnetic layer and a second annular free magnetic layer disposed about the annular non-magnetic layer, the first and second annular free magnetic layers separated by, a non-magnetic separator layer and an annular tunnel insulator disposed about the plurality of annular free magnetic layers and the non-magnetic separator layer;
• a first planar reference magnetic layer disposed about the plurality of annular structures and separated from the free magnetic layers of the plurality of annular structures by the annular tunnel barrier layer of the plurality of annular structures and the first planar reference magnetic layer aligned with the first annular free magnetic layer;
• a first non-magnetic insulator layer disposed about the plurality of annular structures and on a first side of the first planar reference magnetic layer;
• and
• a second non-magnetic insulator layer disposed about the plurality of annular structures and on a second side of the first planar reference magnetic layers;
• a second planar reference magnetic layer disposed about the plurality of annular structures and separated from the free magnetic layers of the plurality of annular structures by the annular tunnel barrier layers of the plurality of annular structures, and the second planar reference magnetic layer aligned with the second annular free magnetic layer;
• a third non-magnetic insulator layer disposed about the plurality of annular structures and between the second non-magnetic insulator layer and a first side of the second planar reference magnetic layer;
• a fourth non-magnetic insulator layer disposed about the plurality of an annular structures and on a second side of the second planar reference magnetic layer
• a first bit line coupled to the first planar reference magnetic layer;
• and
• a second bit line coupled to the second planar reference magnetic layer.