US 2019/0296148 A1Published application

Semiconductor device

AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation

InventorAkihiro Tanaka

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor device of an embodiment includes a first region including a first portion of a semiconductor layer having first and second planes, a first trench, a first gate electrode, a first source electrode and a drain electrode; a second region adjacent to the first region in a first direction and including a second portion of the semiconductor layer, a second trench, a second gate electrode, a second source electrode on the first plane side, and the drain electrode; a third region adjacent to the first region in a second direction crossing the first direction and including a third portion of the semiconductor layer, a third trench, a third gate electrode, a third source electrode on the first plane side, and the drain electrode; a first gate electrode pad connected to the first gate electrode; and a second gate electrode pad connected to the second and third gate electrodes.

Claims10

Dependent claims

A semiconductor device comprising:

a first region including a first portion of a semiconductor layer having a first plane and a second plane, a first trench provided in the first portion, a first gate electrode provided in the first trench, a first source electrode provided on a first plane side of the first portion, and a drain electrode provided on a second plane side of the first portion;
a second region provided to be adjacent to the first region in a first direction and including a second portion of the semiconductor layer, a second trench provided in the second portion, a second gate electrode provided in the second trench, a second source electrode provided on the first plane side of the second portion, and the drain electrode provided on the second plane side of the second portion;
a third region provided to be adjacent to the first region in a second direction crossing the first direction and including a third portion of the semiconductor layer, a third trench provided in the third portion, a third gate electrode provided in the third trench, a third source electrode provided on the first plane side of the third portion, and the drain electrode provided on the second plane side of the third portion;
a first gate electrode pad electrically connected to the first gate electrode;
and
a second gate electrode pad electrically connected to the second gate electrode and the third gate electrode.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/110,332Filed 23 Aug 2018
Priority: JP 2018-05368221 Mar 2018
Published: 26 Sep 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 62/127
Top-view geometrical layouts of the regions or the junctions: of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
H10D 64/252
Source or drain electrodes for field-effect devices: for vertical or pseudo-vertical devices
H10D 64/513
Disposition of the gate electrodes, e.g. buried gates: within recesses in the substrate, e.g. trench gates, groove gates or buried gates