US 2019/0296147 A1Published application

Semiconductor device

AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation

InventorKeiko KAWAMURA

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Abstract

A semiconductor device includes first to third semiconductor layers stacked, and control electrodes provided in trenches extending in a stacking direction. The device further includes an insulating region and a fourth semiconductor layer. The insulating region is provided between first and second control electrodes adjacent to each other. The fourth semiconductor layer is provided between the insulating region and the first and second control electrodes, and between the insulating region and the first semiconductor layer. A first insulating film is provided between the first control electrode and the fourth semiconductor layer, and contacts the first control electrode and the fourth semiconductor layer. A second insulating film is provided between the second control electrode and the fourth semiconductor layer, and contacts the second control electrode and the fourth semiconductor layer. The insulating region has an end positioned at a level lower than a level of ends of the control electrodes.

Claims20

Dependent claims

A semiconductor device, comprising:

a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;
a third semiconductor layer of the first conductivity type provided on the second semiconductor layer;
a plurality of control electrodes provided respectively in a plurality of trenches, the plurality of trenches having depths into the first semiconductor layer from a top surface of the third semiconductor layer, the plurality of control electrodes having ends positioned in the first semiconductor layer;
an insulating region provided between a first control electrode and a second control electrode of the plurality of control electrodes, the first control electrode and the second control electrode being adjacent to each other in a first direction along an interface between the first semiconductor layer and the second semiconductor layer, the insulating region extending in a second direction from the third semiconductor layer toward the first semiconductor layer, the insulating region having an end positioned in the first semiconductor layer, the end of the insulating region being positioned at a level in the second direction lower than the level in the second direction of the ends of the plurality of control electrodes;
a fourth semiconductor layer of the second conductivity type provided between the insulating region and the first semiconductor layer, between the insulating region and the first control electrode, and between the insulating region and the second control electrode;
a first insulating film provided between the first control electrode and the fourth semiconductor layer, the fourth semiconductor layer being in contact with a whole portion of the first insulating film positioned between the first control electrode and the fourth semiconductor layer;
a second insulating film provided between the second control electrode and the fourth semiconductor layer, the fourth semiconductor layer being in contact with a whole portion of the second insulating film positioned between the second control electrode and the fourth semiconductor layer;
and
a first electrode connected to the third semiconductor layer and the fourth semiconductor layer.

7 more elements

A semiconductor device, comprising:

a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;
a third semiconductor layer of the first conductivity type provided on the second semiconductor layer;
an insulating region extending in the first semiconductor layer from a top surface of the third semiconductor layer, the insulating region having a bottom end in the first semiconductor layer;
a control electrode provided in a trench between the third semiconductor layer and the insulating region, the trench surrounding the insulating region and having a depth into the first semiconductor layer from the top surface of the third semiconductor layer, the control electrode having a bottom end in the first semiconductor layer, the bottom end of the insulating region being positioned at a level deeper than a level of the bottom end of the control electrode;
a fourth semiconductor layer of the second conductivity type provided between the insulating region and the first semiconductor layer and between the insulating region and the control electrode;
an insulating film provided between the control electrode and the fourth semiconductor layer, the fourth semiconductor layer being in contact with a whole portion of the insulating film positioned between the control electrode and the fourth semiconductor layer;
and
a first electrode connected to the third semiconductor layer and the fourth semiconductor layer.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/106,360Filed 21 Aug 2018
Priority: JP 2018-05479822 Mar 2018
Published: 26 Sep 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 30/665
Vertical dmos [vdmos] fets: having edge termination structures
H10D 62/058
Forming charge compensation regions, e.g. superjunctions: by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches