US 2019/0296142 A1Published application

Two Step Fin Etch and Reveal for VTFETs and High Breakdown LDVTFETs

AssigneeInternational Business Machines Corporation

InventorsMona Ebrish, Xuefeng Liu, Brent Anderson, Huiming Bu, Junli Wang

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Abstract

High breakdown voltage devices are provided. In one aspect, a method of forming a device having a VTFET and a LDVTFET includes: forming a LDD in an LDVTFET region; patterning fin(s) in a VTFET region to a depth D1; patterning fin(s) in the LDVTFET region, through the LDD, to a depth D2>D1; forming bottom source/drains at a base of the VTFET/LDVTFET fins; burying the VTFET/LDVTFET fins in a gap fill dielectric; recessing the gap fill dielectric to full expose the VTFET fin(s) and partially expose the LDVTFET fin(s); forming bottom spacers directly on the bottom source/drains in the VTFET region and directly on the gap fill dielectric in the LDVTFET region; forming gates alongside the VTFET/LDVTFET fins; forming top spacers above the gates; and forming top source/drains above the top spacers. A one-step fin etch and devices having VTFET and long channel VTFETs are also provided.

Claims20

Dependent claims

A method of forming a device having a vertical fin field-effect transistor (VTFET) and a lateral diffusion VTFET (LDVTFET), the method comprising the steps of:

forming a lightly-doped drain (LDD) in an LDVTFET region of a wafer;
selectively patterning at least one fin in a VTFET region of the wafer to a depth D1;
selectively patterning at least one fin in the LDVTFET region of the wafer, through the LDD, to a depth D2, wherein D2>D1;
forming bottom source and drains at a base of the at least one fin in the VTFET region and the at least one fin in the LDVTFET region;
burying the at least one fin in the VTFET region and the at least one fin in the LDVTFET region in a gap fill dielectric;
recessing the gap fill dielectric to fully expose the at least one fin in the VTFET region and partially expose the at least one fin in the LDVTFET region;
forming bottom spacers directly on the bottom source and drains in the VTFET region of the wafer and directly on the recessed gap fill dielectric in the LDVTFET region of the wafer;
forming gates alongside the at least one fin in the VTFET region and the at least one fin in the LDVTFET region above the bottom spacers;
forming top spacers above the gates;
and
forming top source and drains above the top spacers at tops of the at least one fin in the VTFET region and the at least one fin in the LDVTFET region.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/927,962Filed 21 Mar 2018
Published: 26 Sep 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 84/013
The components including insulated gates, e.g. IGFETs: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/141
Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode: vDMOS having built-in components
H10D 30/022
Of FETs having insulated gates [IGFET]: having lightly-doped source or drain extensions selectively formed at the sides of the gates
H10D 30/025
Of FETs having insulated gates [IGFET]: of vertical IGFETs