Method of forming gate spacer for nanowire fet device

A method of forming a gate-all-around semiconductor device, comprising:

• providing a substrate having a layered fin structure thereon, the layered fin structure comprising a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material;
• forming a dummy gate on said replacement gate material over said layered fin structure, wherein the dummy gate having a critical dimension which extends along said length of the layered fin structure;
• and
• forming a gate structure directly under said dummy gate, said gate structure comprising a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein said gate spacers are formed by etching to undercut ends of said dummy gate to form lateral recesses in opposing sidewall surfaces of the layered fin structure and then filling the lateral recesses with a gate spacer material.

A gate all around nanowire FET device comprising:

• at least one nanowire having opposing ends;
• a gate structure comprising a metal gate region surrounding a middle portion of the at least one nanowire, and gate spacers surrounding remaining end portions of the nanowire to form opposing sidewalls of the gate structure, such that the gate structure is coextensive with the nanowire in a direction running from one of the opposing sidewalls to another of the opposing sidewalls;
• and
• source-drain regions provided on said opposing sidewalls of the gate structure.