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US 2019/0296120 A1Published application
Asymmetric high-k dielectric for reducing gate induced drain leakage
AssigneeInternational Business Machines Corporation
InventorsAnthony I. CHOU, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
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Abstract
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
Claims13
A gate structure comprising:
- a gate structure comprising an asymmetrically thick gate dielectric which is thicker on a drain side of the gate structure than a source side of the gate structure;
- a damaged spacer material on the drain side of the gate structure along a sidewall of the gate structure;
- and
- a non-damaged spacer material on the source side of the gate structure along another sidewall of the gate structure.
1 more element
Dependencies are inferred from the claim text.