Semiconductor device having polysilicon field plate for power mosfets

A method of fabricating a semiconductor device, comprising:

• forming a trench for a field plate (FP) in a semiconductor surface layer of a substrate;
• dielectric lining the trench with a dielectric liner including a first dielectric liner layer and then depositing a second dielectric liner layer on the first dielectric liner layer;
• coating the substrate with photoresist (PR) including filling the trench;
• exposing and then developing the PR to remove the PR in an upper portion of the trench so that the PR remains in a lower portion of the trench;
• etching to remove the second dielectric liner layer in the upper portion of the trench, wherein the second dielectric liner layer and the first dielectric liner layer in the lower portion of the trench are both protected by the PR;
• stripping the PR;
• filling the trench by depositing a single polysilicon layer, and
• forming a power metal-oxide-semiconductor field effect transistor (power MOSFET) adjacent to the FP, the power MOSFET including a vertical drift region in the semiconductor surface layer above a drain including a drain contact, a gate, a body, and a source above the vertical drift region.

A semiconductor device, comprising:

• a substrate including a semiconductor surface layer;
• a field plate (FP) comprising a trench in the semiconductor surface layer filled with a single polysilicon layer on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET), the FP comprising:
• a dielectric liner lining a sidewall of the trench under the single polysilicon layer comprising a second dielectric liner on a first dielectric liner, an upper portion of the dielectric liner having a lower dielectric thickness as compared to a dielectric thickness on a lower portion of the dielectric liner,
• wherein the single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion, and
• wherein the power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, a body and a source above the vertical drift region.