US 2019/0296114 A1 · NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME

Abstract

Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Claims16

Dependent claims

A method of fabricating a semiconductor device, the method comprising:

forming a plurality of semiconductor fins above a semiconductor substrate;
forming a catalyst layer above the semiconductor substrate, conformal with the plurality of semiconductor fins;
forming a mask above the catalyst layer;
recessing the mask and the catalyst layer to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins;
oxidizing outer portions of the sub-fin regions of each of the plurality of semiconductor fins using the catalyst layer to catalytically oxidize the sub-fin regions;
and
removing oxide formed from the oxidizing to provide a plurality of omega-fins having sub-fin regions narrower than corresponding protruding proportions.

4 more elements

A method of fabricating an integrated structure, the method comprising:

forming a first fin comprising a silicon material, the first fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion;
forming a second fin comprising the silicon material, the second fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion;
forming a layer comprising a phosphosilicate glass (PSG), the layer comprising the PSG directly on sidewalls of the lower fin portion of the first fin and directly on sidewalls of the lower fin portion of the second fin, the layer comprising the PSG having a first end portion substantially co-planar with the shoulder feature of the first fin, and the layer comprising the PSG having a second end portion substantially co-planar with the shoulder feature of the second fin;
forming an insulating layer comprising nitrogen, the insulating layer directly on the layer comprising the PSG;
forming a dielectric fill material directly laterally adjacent to the insulating layer;
and
forming a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, and the gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the second fin, and the gate electrode over the dielectric fill material between the first fin and the second fin.

4 more elements

A method of fabricating an integrated structure, the method comprising:

forming a first fin comprising a silicon material, the first fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion;
forming a second fin comprising the silicon material, the second fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion;
forming a dielectric layer comprising an N-type dopant, the dielectric layer directly on sidewalls of the lower fin portion of the first fin and directly on sidewalls of the lower fin portion of the second fin, the dielectric layer having a first end portion substantially co-planar with the shoulder feature of the first fin, and the dielectric layer having a second end portion substantially co-planar with the shoulder feature of the second fin;
forming an insulating layer comprising nitrogen, the insulating layer directly on the dielectric layer;
forming a dielectric fill material directly laterally adjacent to the insulating layer;
and
forming a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, and the gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the second fin, and the gate electrode over the dielectric fill material between the first fin and the second fin.

4 more elements

Dependencies are inferred from the claim text.

Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same

Life of this patent

Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same

Life of this patent

Abstract

Claims16