Dielectric and isolation lower fin material for fin-based electronics
AssigneeIntel Corporation
InventorsWalid M. HAFEZ, Chia-Hong JAN
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Abstract
A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.
Claims20
A method comprising:
- forming a fin on a substrate;
- depositing a glass of a first dopant type over the substrate and over a lower portion of the fin;
- depositing a glass of a second dopant type over the substrate and the fin;
- annealing the glass to drive the dopants into the fin and the substrate;
- removing the glass;
- and
- forming a first and a second contact over the fin without contacting the lower portion of the fin.
A method of fabricating an integrated circuit structure, the method comprising:
- forming a fin comprising silicon, the fin having a lower fin portion and an upper fin portion;
- forming a layer comprising a phosphosilicate glass (PSG), the layer comprising the PSG directly on first and second sidewalls of the lower fin portion of the fin, the layer comprising the PSG having a first upper end portion laterally adjacent to the first sidewall of the lower fin portion of the fin, and the layer comprising the PSG having a second upper end portion laterally adjacent to the second sidewall of the lower fin portion of the fin;
- forming an isolation material comprising oxygen, the isolation material laterally adjacent to the layer comprising the PSG directly on the first and second sidewalls of the lower fin portion of the fin, the isolation material having a first upper surface portion and a second upper surface portion, wherein the first upper surface portion of the isolation material is below the first upper end portion of the layer comprising the PSG, and wherein the second upper surface portion of the isolation material is below the second upper end portion of the layer comprising the PSG;
- and
- forming a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the fin, and the gate electrode over the first and second upper end portions of the layer comprising the PSG, and the gate electrode over the first and second upper surface portions of the isolation material.
A method of fabricating an integrated circuit structure, the method comprising:
- forming a fin comprising silicon, the fin having a lower fin portion and an upper fin portion;
- forming a dielectric layer comprising a P-type dopant, the dielectric layer directly on first and second sidewalls of the lower fin portion of the fin, the dielectric layer having a first upper end portion laterally adjacent to the first sidewall of the lower fin portion of the fin, and the dielectric layer having a second upper end portion laterally adjacent to the second sidewall of the lower fin portion of the fin;
- forming an isolation material comprising oxygen, the isolation material laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin portion of the fin, the isolation material having a first upper surface portion and a second upper surface portion, wherein the first upper surface portion of the isolation material is below the first upper end portion of the dielectric layer, and wherein the second upper surface portion of the isolation material is below the second upper end portion of the dielectric layer;
- and
- forming a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the fin, and the gate electrode over the first and second upper end portions of the dielectric layer, and the gate electrode over the first and second upper surface portions of the isolation material.
Dependencies are inferred from the claim text.