US 2019/0296064 A1 · PACKAGING METHOD AND PACKAGING STRUCTURE FOR SEMICONDUCTOR CHIP

Abstract

Provided are a packaging method and packaging structure for a semiconductor chip. The packaging method comprises: providing a wafer, the wafer being provided with multiple semiconductor chips, each semiconductor chip being provided with a functional area and solder pads arranged on a first surface; providing a protective substrate, multiple support units being provided on the protective substrate, openings being formed on the support units; aligning the solder pads to the openings and facing support units provided on the protective substrate to the first surface of the wafer, and pressing together the wafer and the protective substrate. The packaging method effectively prevents the support units from generating stress that acts on the solder pads in a subsequent reliability test, thus preventing cases of the solder pad being damaged or split into layers.

Claims20

Dependent claims

A semiconductor chip packaging method, comprising:

providing a wafer having a first surface and a second surface opposite to each other, wherein the wafer comprises a plurality of semiconductor chips, and each of the plurality of semiconductor chips comprises a functional region and contact pads arranged on the first surface;
providing a protective substrate, wherein one surface of the protective substrate is arranged with a plurality of support units, and each of the plurality of support units is provided with openings;
and
laminating the wafer with the protective substrate in a manner that each of the contact pads is aligned with one opening and each of the plurality of support units on the protective substrate is arranged facing the first surface of the wafer.

1 more element

A semiconductor chip package, comprising:

a substrate having a first surface and a second surface opposite to each other;
a functional region and contact pads arranged on the first surface of the substrate;
a protective substrate arranged on the first surface of the substrate;
and
a support unit arranged between the protective substrate and the substrate, wherein the functional region is arranged in a sealed cavity formed by surrounding the support unit, and the support unit is provided with openings, wherein a first surface of a wafer is not in contact with the support unit at a position corresponding to each of the contact pads.

2 more elements

Dependencies are inferred from the claim text.

Packaging method and packaging structure for semiconductor chip

Life of this patent

Packaging method and packaging structure for semiconductor chip

Life of this patent

Abstract

Claims20