Accommodating imperfectly aligned memory holes
AssigneeApplied Materials, Inc.
InventorVinod R. Purayath
Life of this patent
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AssigneeApplied Materials, Inc.
InventorVinod R. Purayath
Estimating the term…
Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. Two options for completing the methods include (1) forming a ledge spacer to allow reactive ion etching of the bottom polysilicon portion without damaging polysilicon or charge-trap/ONO layer on the ledge, and (2) placing sacrificial silicon oxide gapfill in the bottom memory hole, selectively forming protective conformal silicon nitride elsewhere, then removing the sacrificial silicon oxide gapfill before performing the reactive ion etching of the bottom polysilicon portion as before.
A method of forming a memory cell, the method comprising:
A method of forming a memory cell, the method comprising:
A method of forming a memory cell, the method comprising:
Dependencies are inferred from the claim text.