Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsShuto YAMASAKA, Tomonori AOYAMA
Life of this patent
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Abstract
According to one embodiment, a semiconductor memory device includes a circuitry layer, first conductive layers, a pillar layer, and a second conductive layer. The circuitry layer is provided on a substrate and includes a CMOS circuit. The first conductive layers are provided above the circuitry layer, and are stacked with an insulation layer interposed therebetween. The pillar layer crosses the first conductive layers, and includes silicon single crystal. The second conductive layer is provided on the pillar layer and includes silicon single crystal containing impurities. The first conductive layers are provided between the circuitry layer and the second conductive layer.
Claims20
A semiconductor memory device comprising:
- a circuitry layer provided on a substrate and including a CMOS circuit;
- first conductive layers provided above the circuitry layer, and stacked with an insulation layer interposed therebetween;
- a pillar layer crossing the first conductive layers, and including silicon single crystal;
- and
- a second conductive layer provided on the pillar layer and including silicon single crystal containing impurities,
- wherein the first conductive layers are provided between the circuitry layer and the second conductive layer.
A semiconductor memory device comprising:
- first conductive layers stacked with an insulation layer interposed therebetween;
- a pillar layer crossing the first conductive layers, and including silicon single crystal;
- a source line including a stacked structure of a metal silicide layer and a silicon single crystal layer containing impurities, a first end of the pillar layer being in contact with the silicon single crystal layer;
- and
- a circuitry layer including a CMOS circuit electrically connected to a second end of the pillar layer.
A method of manufacturing a semiconductor memory device comprising:
- forming a first silicon single crystal layer on a first substrate;
- forming a stacked film in which a plurality of first films and a plurality of second films are alternately stacked above the first silicon single crystal layer;
- forming a hole that passes through the stacked film along a stacking direction of the stacked film and reaches the first silicon single crystal layer;
- forming a cell insulation layer on an inner wall of the hole;
- and
- forming a second silicon single crystal layer on an inner wall of the cell insulation layer in the hole;
- forming a first conductive pad above the second silicon single crystal layer;
- forming a CMOS circuit including an n-channel MOS transistor and a p-channel MOS transistor on a second substrate;
- forming a second conductive pad above the CMOS circuit;
- and
- bonding the first substrate and the second substrate to each other such that the first conductive pad faces the second conductive pad.
Dependencies are inferred from the claim text.