Semiconductor memory device

A semiconductor memory device, comprising:

• a substrate including an upper surface;
• a stacked body provided above the upper surface, the stacked body including a plurality of electrode layers stacked to be separated from each other;
• a plurality of columnar portions extending through the stacked body in a stacking direction of the electrode layers, the columnar portions including a first columnar portion and a second columnar portion, the first columnar portion including a first semiconductor portion, the second columnar portion including a second semiconductor portion;
• a plurality of interconnects extending in a first direction parallel to the upper surface, the stacked body being provided between the upper surface and the interconnects, the interconnects including a first interconnect and a second interconnect next to the first interconnect, the first interconnect being electrically connected to the first semiconductor portion, the second interconnect being electrically connected to the second semiconductor portion;
• a first connection portion, at least a part of the first connection portion being provided between the first semiconductor portion and the first interconnect, the first connection portion electrically connecting the first semiconductor portion with the first interconnect;
• and
• a second connection portion, at least a part of the second connection portion being provided between the second semiconductor portion and the second interconnect, the second connection portion electrically connecting the second semiconductor portion with the second interconnect, wherein
• a portion of the first connection portion overlaps the second connection portion in a second direction crossing the first direction and being parallel to the upper surface, and
• the first columnar portion does not overlap the second columnar portion in the second direction.