Integrated Circuit Constructions Comprising Memory And Methods Used In The Formation Of Integrated Circuitry Comprising Memory

An integrated circuit construction comprising memory, comprising:

• two memory-cell-array regions having a peripheral-circuitry region laterally there-between in a vertical cross-section, the two memory-cell-array regions individually comprising:
• a plurality of capacitors individually comprising a capacitor storage node electrode, a shared capacitor electrode that is shared by the plurality of capacitors, and a capacitor insulator there-between;
• and
• a laterally-extending insulator structure that is about lateral peripheries of the capacitor storage node electrodes and that is vertically spaced from a top and a bottom of individual of the capacitor storage node electrodes in the vertical cross-section;
• and
• the peripheral-circuitry region in the vertical cross-section comprising:
• a pair of elevationally-extending walls comprising a first insulative composition;
• a second insulative composition different from the first insulative composition laterally between the pair of walls;
• and
• the pair of walls individually having a laterally-outer side of the first insulative composition that is directly against the capacitor insulator in different ones of the two array regions, the pair of walls individually having a laterally-inner side of the first insulative composition that is directly against different ones of two lateral sides of the second insulative composition.

An integrated circuit construction comprising memory, comprising:

• a memory-cell-array region and a peripheral-circuitry region laterally adjacent thereto in a vertical cross-section, the memory-cell-array region comprising:
• a plurality of capacitors individually comprising a capacitor storage node electrode, a shared capacitor electrode that is shared by the plurality of capacitors, and a capacitor insulator there-between;
• and
• a laterally-extending insulator structure that is about lateral peripheries of the capacitor storage node electrodes and that is vertically spaced from a top and a bottom of individual of the capacitor storage node electrodes in the vertical cross-section;
• and
• the laterally-extending insulator structure having a lateral edge proximate the peripheral-circuitry region in the vertical cross-section, the lateral edge being laterally spaced from the peripheral circuitry region, conductive material of the shared capacitor electrode being laterally between the lateral edge and the peripheral-circuitry region.

An integrated circuit construction comprising memory, comprising:

• two memory-cell-array regions having a peripheral-circuitry region laterally there-between in a vertical cross-section, the two memory-cell-array regions individually comprising:
• a plurality of capacitors individually comprising a capacitor storage node electrode, a shared capacitor electrode that is shared by the plurality of capacitors, and a capacitor insulator there-between;
• and
• a laterally-extending insulator structure that is about lateral peripheries of the capacitor storage node electrodes and that is vertically spaced from a top and a bottom of individual of the capacitor storage node electrodes in the vertical cross-section;
• and
• the peripheral-circuitry region in the vertical cross-section comprising:
• a pair of elevationally-extending walls comprising a first insulative composition;
• a second insulative composition different from the first insulative composition laterally between the pair of walls;
• and
• the pair of walls individually having a laterally-outer side of the first insulative composition that is directly against a lateral edge of the insulator structure that is in different ones of the two array regions.