Cmos devices containing asymmetric contact via structures and method of making the same

A method of forming a semiconductor structure, comprising:

• forming a combination of a p-type field effect transistor including p-doped active regions, and n-type field effect transistor including n-doped active regions on a semiconductor substrate;
• forming a silicon oxide liner, a silicon nitride liner, and a planarization silicon oxide layer that overlie the p-type field effect transistor and the n-type field effect transistor;
• forming a patterned dielectric material layer that covers an entirety of an area of the n-type field effect transistor and does not cover at least a fraction of each area of the p-doped active regions over the semiconductor substrate;
• simultaneously forming p-type active region via cavities over the p-doped active regions and n-type active region via cavities over the n-doped active regions employing a first anisotropic etch process, wherein the p-type active region via cavities extend to a respective top surface of the p-doped active regions, and the n-type active region via cavities have a respective bottom surface at, or within, one of the silicon nitride liner and the silicon oxide liner;
• forming boron-doped epitaxial pillar structures epitaxially aligned to the p-doped active regions on top surfaces of the p-type active regions employing a selective epitaxy process;
• extending the n-type active region via cavities to top surfaces of the n-doped active regions;
• and
• forming contact via structures at least in the p-type active region via cavities and the n-type active region via cavities.