Means for reducing finfet parasitic resistance

Abstract

A device structure for reducing FinFET parasitic resistance and a manufacturing method thereof. The method comprises preparing a FinFET device like conventional FinFET structure, including preparing a FinFET silicon fin, forming a gate stack consisting of a gate electrode and a gate dielectric layer, and defining a source-drain region of the FinFET device; wherein the gate stack, which formed by the gate electrode and the gate dielectric layer in the FinFET device, wraps the FinFET silicon fin from the two sides and the surface respectively, to form a three-dimensional channel of the MOSFET; preparing a catalyst layer in the source-drain region; growing a carbon nanotube, to form a strip-shaped contact hole layer M0; wherein, the lower end of the strip-shaped contact hole layer M0 covers and connects the source-drain region of the FinFET device; the material of the strip-shaped contact hole layer M0 is a single-wall carbon nanotube or multi-wall carbon nanotube; and achieving the source-drain region connecting-out and the back-end process for preparation of the FinFET device, wherein the upper end of the strip-shaped contact hole layer M0 is connected to the metal layer M1.

Dependencies are inferred from the claim text.