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US 2019/0296007 A1Published application
Method for fabricating a jfet transistor within an integrated circuit and corresponding integrated circuit
AssigneeSTMicroelectronics (Crolles 2) SAS
InventorJean JIMENEZ
Life of this patent
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Abstract
An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography. A gate region of the transistor is formed by two spaced apart first trenches in that are filled with a doped semiconductor material, wherein the two spaced apart first trenches bound the channel region and set the critical dimension.
Claims18
An integrated circuit, including at least one vertical junction field-effect transistor, comprising:
- a semiconductor well of a first type of conductivity;
- a drain region comprising a buried layer of the first type of conductivity having a doping level that is higher than a doping level of the semiconductor well;
- a contact well of the first type of conductivity that extends from a surface of the semiconductor well down to the buried layer;
- a gate region comprising two spaced apart first trenches in that are filled with a semiconductor material of a second type of conductivity, said two spaced apart first trenches bounding a channel region;
- and
- a source region of the first type of conductivity on top of the semiconductor well at an active surface of the channel region.
3 more elements
Dependencies are inferred from the claim text.