Embedded chip package, manufacturing method thereof, and package-on-package structure

A manufacturing method of an embedded chip package, comprising:

• providing a carrier and a release layer disposed on the carrier;
• disposing a chip on the release layer;
• disposing a circuit board on the release layer, the circuit board comprising:
• a glass substrate having a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate;
• and
• at least one conductive via penetrating the glass substrate;
• forming a dielectric material layer on the release layer after the chip and the circuit board are disposed on the release layer and the chip is embedded inside the through-hole, wherein the dielectric material layer is filled inside the through-hole and covers the chip;
• removing the release layer and the carrier to expose a lower surface of the chip outside the dielectric material layer;
• and
• forming a build-up circuit structure on the circuit board after the release layer and the carrier are removed such that the build-up circuit structure is electrically connected to the conductive via.